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Mostrando ítems 1-5 de 5
Artículo
1 V CMOS subthreshold log domain PDM
(Springer, 2003)
A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing ...
Ponencia
A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology
(2000)
This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, ...
Artículo
Low-voltage CMOS log-companding techniques for audio applications
(Springer, 2004)
This paper presents a collection of novel current-mode circuit techniques for the integration of very low-voltage (down to 1 V) low-power (few hundreds of μA) complete SoCs in CMOS technologies. The new design proposal is ...
Ponencia
Selection of test techniques for high-resolution ΣΔ modulators
(2000)
This paper introduces a new tool which allows the evaluation of different test techniques in a complete impartial manner. This tool has been applied to the selection of the best test technique for their application to ...
Artículo
Analysis of error mechanisms in switched-current Sigma-Delta modulators
(Springer, 2004)
This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, ...