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Mostrando ítems 21-30 de 47
Artículo
A general translinear principle for subthreshold MOS transistors
(Institute of Electrical and Electronics Engineers, 1999)
This paper revises the conditions under which the translinear principle can be fully exploited for MOS transistors operating in subthreshold. Due to the exponential nature of subthreshold MOS transistors, the translinear ...
Ponencia
Red neuronal convolucional rápida sin fotogramas para reconocimientos de dígitos
(Unión Científica Internacional de Radio, 2011)
In this paper a bio-inspired six-layer convolutional network (ConvNet) non-frame based for digit recognition is shown. The system has been trained with the backpropagation algorithm using 32x32 images from the MNIST ...
Artículo
A precise 90º quadrature OTA-C oscillator tunable in the 50-130-MHz range
(Institute of Electrical and Electronics Engineers, 2004)
We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-μm CMOS process. The oscillator is tunable in the ...
Ponencia
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
(Neural Information Processing Systems Foundation, 2005)
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-eventrepresentation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a ...
Artículo
Fast vision through frameless event-based sensing and convolutional processing: Application to texture recognition
(Institute of Electrical and Electronics Engineers, 2010)
Address-event representation (AER) is an emergent hardware technology which shows a high potential for providing in the near future a solid technological substrate for emulating brain-like processing structures. When used ...
Artículo
An ART1 microchip and its use in multi-ART1 systems
(Institute of Electrical and Electronics Engineers, 1997)
Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. Such chip is able to cluster 100-b patterns into up to 18 categories at a speed of 1.8 μs per pattern. However, ...
Artículo
Hardware Implementation of Differential Oscillatory Neural Networks Using VO 2-Based Oscillators and Memristor-Bridge Circuits
(Frontiers Media, 2021)
Oscillatory Neural Networks (ONNs) are currently arousing interest in the research community for their potential to implement very fast, ultra-low-power computing tasks by exploiting specific emerging technologies. From ...
Artículo
Multi-casting mesh AER: A scalable assembly approach for reconfigurable neuromorphic structured AER systems. Application to ConvNets
(Institute of Electrical and Electronics Engineers, 2013)
This paper presents a modular, scalable approach to assembling hierarchically structured neuromorphic Address Event Representation (AER) systems. The method consists of arranging modules in a 2D mesh, each communicating ...
Artículo
The active-input regulated-cascode current mirror
(Institute of Electrical and Electronics Engineers, 1994)
A continuous-time current mirror circuit is presented that combines an active input and a regulated cascode output. The current mirror offers a high accuracy over an operating current range higher than previous structures. ...
Artículo
Comparison between frame-constrained fix-pixel-value and frame-free spiking-dynamic-pixel convNets for visual processing
(Frontiers Media, 2012)
Most scene segmentation and categorization architectures for the extraction of features in images and patches make exhaustive use of 2D convolution operations for template matching, template search, and denoising. Convolutional ...