Buscar
Mostrando ítems 11-20 de 56
Ponencia
Transformer based front-end for a low power 2.4 GHz transceiver
(Institute of Electrical and Electronics Engineers, 2010)
A low power transceiver architecture for the 2.4 GHz ISM band using a 1.0 V supply is presented. It employs a transformer to convert the 100 Ω antenna impedance to almost 1 kΩ and so facilitates a low power transmitter and ...
Ponencia
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends for neural recording applications. These techniques are employed for handling Common-Mode (CM) ...
Artículo
A mixed-signal integrated circuit for FM-DCSK modulation
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental ...
Ponencia
Experimental verification of chaotic encryption of audio using monolithic chaotic modulators
(SPIE- The International Society for Optical Engineering, 1995)
This paper reports the first experimental verification of chaotic encryption of audio signals using integrated circuits. It is based on a g m-C modulator/demodulator analog CMOS IC that implements a 3rd-order nonlinear ...
Ponencia
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design
(Institute of Electrical and Electronics Engineers, 1999)
This paper describes ESPRIT 29648, concerning the development of an advanced methodology for the design of a mixed-signal application-driven quadrature D/A interface sub-system, aiming at its reusability by a retargetting ...
Artículo
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
(Institute of Electrical and Electronics Engineers, 2011)
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the ...
Artículo
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits
(Institute of Electrical and Electronics Engineers, 2009)
We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the ...
Ponencia
IC design for spread spectrum communication exploiting chaos
(Institute of Electrical and Electronics Engineers, 1996)
This paper presents a 2.4 /spl mu/m CMOS IC prototype which includes a programmable chaotic generator and some interface circuitry for chaotic encryption. It realizes a member of the family of the canonical Chua's state ...
Ponencia
A 4-mode reconfigurable low noise amplifier for implantable neural recording channels
(Institute of Electrical and Electronics Engineers, 2016)
In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture ...
Artículo
A Chaotic Switched-Capacitor Circuit for 1/f Noise Generation
(Institute of Electrical and Electronics Engineers, 1992)
A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order piecewise-finear discrete map which yields a hopping transition between regions of chaotic motions ...