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Mostrando ítems 1-10 de 17
Artículo
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose ...
Ponencia
Discrete-time integrated circuits for chaotic communication
(Institute of Electrical and Electronics Engineers, 1997)
This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital filter structures with overflow non-linearity. Simulation results from an integrated prototype using ...
Ponencia
An algorithm for numerical reference generation in symbolic analysis of large analog circuits
(Institute of Electrical and Electronics Engineers, 1997)
This paper addresses the problems arising in the calculation of numerical references (network function coefficients), essential for an appropriate error control in simplification before and during generation algorithms for ...
Ponencia
Ponencia
Design of a programmable mixed-signal CMOS image-processing chip in 0.8 /spl mu/m CMOS
(Institute of Electrical and Electronics Engineers, 1997)
An operational vision-chip prototype with a wide-range of potential applications in artificial-vision systems is presented. Its functionality includes concurrent image-transduction, programmable image-processing, image-storage, ...
Artículo
Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology
(Wiley-Blackwell, 1997)
This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an ...
Artículo
Robust high-accuracy high-speed continuous-time CMOS current comparator
(Institution of Engineering and Technology, 1997)
The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5pA) and high-speed for low input currents (8ns at 50nA). The new structure features a speed ...
Ponencia
A modular CMOS analog fuzzy controller
(Institute of Electrical and Electronics Engineers, 1997)
The low/medium precision required for many fuzzy applications makes analog circuits natural candidates to design fuzzy chips with optimum speed/power figures. This paper presents a sixteen rules-two inputs analog fuzzy ...
Artículo
An ART1 microchip and its use in multi-ART1 systems
(Institute of Electrical and Electronics Engineers, 1997)
Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. Such chip is able to cluster 100-b patterns into up to 18 categories at a speed of 1.8 μs per pattern. However, ...
Ponencia
Mismatch distance term compensation in centroid configurations with nonzero-area devices
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents an analytical approach to distance term compensation in mismatch models of integrated devices. Firstly, the conditions that minimize parameter mismatch are examined under the assumption of zero-area ...