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Mostrando ítems 1-10 de 11
Artículo
Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction
(Institute of Electrical and Electronics Engineers, 2017)
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale invariance, which permits having ...
Ponencia
Switched-capacitor networks for scale-space generation
(Institute of Electrical and Electronics Engineers, 2011)
In scale-space filtering signals are represented at several scales, each conveying different details of the original signal. Every new scale is the result of a smoothing operator on a former scale. In image processing, ...
Ponencia
In-pixel generation of gaussian pyramid images by block reusing in 3D-CMOS
(Institute of Electrical and Electronics Engineers, 2012)
This paper introduces an architecture of a switched-capacitor network for Gaussian pyramid generation. Gaussian pyramids are used in modern scale- and rotation-invariant feature detectors or in visual attention. Our ...
Ponencia
Form Factor Improvement of Smart-Pixels for Vision Sensors through 3-D Vertically- Integrated Technologies
(Institute of Electrical and Electronics Engineers, 2014)
While conventional CMOS active pixel sensors embed only the circuitry required for photo-detection, pixel addressing and voltage buffering, smart pixels incorporate also circuitry for data processing, data storage and ...
Ponencia
Gaussian Pyramid Extraction with a CMOS Vision Sensor
(Institute of Electrical and Electronics Engineers, 2014)
This paper addresses a CMOS vision sensor with 176 × 120 pixels in standard 0.18 μm CMOS technology that computes the Gaussian pyramid. The Gaussian pyramid is extracted with a double-Euler switched-capacitor network, ...
Ponencia
In the quest of vision-sensors-on-chip: Pre-processing sensors for data reduction
(Society for Imaging Science and Technology, 2017)
This paper shows that the implementation of vision systems benefits from the usage of sensing front-end chips with embedded pre-processing capabilities - called CVIS. Such embedded pre-processors reduce the number of data ...
Ponencia
Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture ...
Artículo
CMOS-3D smart imager architectures for feature detection
(Institute of Electrical and Electronics Engineers, 2012)
This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers ...
Ponencia
In-pixel ADC for a vision architecture on CMOS-3D technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne surveillance and reconnaissance applications. The 3D chip architecture comprises a sensor layer with a ...
Capítulo de Libro
Image Feature Extraction Acceleration
(Springer, 2016)
Image feature extraction is instrumental for most of the best-performing algorithms in computer vision. However, it is also expensive in terms of computational and memory resources for embedded systems due to the need of ...