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Artículo
Background Digital Calibration of Comparator Offsets in Pipeline ADCs
(Institute of Electrical and Electronics Engineers, 2015)
This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage ...
Artículo
Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
(Institute of Electrical and Electronics Engineers, 2014)
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to ...
Ponencia
A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications
(2008)
This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The ...
Ponencia
Random chopping in ΣΔ modulators
(2009)
Σ∆ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency range. As a result Σ∆ modulators are often the preferred option for ...