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Mostrando ítems 531-540 de 600
Artículo
A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology
(Institute of Electrical and Electronics Engineers, 1999)
This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, ...
Ponencia
A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation
(Institute of Electrical and Electronics Engineers, 2017)
A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise ...
Ponencia
Some design trade-offs for large CNN chips using small-size transistors
(Institute of Electrical and Electronics Engineers, 1997)
Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular Neural Network (CNN) chips. The inverse dependency of mismatch with transistor sizes may result in ...
Ponencia
El Entorno: Vision - E Laboratory
(2010)
Se presenta un entorno de programación para el estudio y desarrollo de algoritmos de tratamiento de imágenes y visión por computador. La herramienta permite la programación en cualquier lenguaje, con la única restricción ...
Ponencia
Random chopping in ΣΔ modulators
(2009)
Σ∆ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency range. As a result Σ∆ modulators are often the preferred option for ...
Artículo
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
(Institute of Electrical and Electronics Engineers, 2017)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this ...
Ponencia
CMOS circuit implementations for neuron models
(Institute of Electrical and Electronics Engineers, 1990)
The mathematical neuron basic cells used as basic cells in popular neural network architectures and algorithms are discussed. The most popular neuron models (without training) used in neural network architectures and ...
Artículo
Efficient feedforward categorization of objects and human postures with address-event image sensors
(Institute of Electrical and Electronics Engineers, 2012)
This paper proposes an algorithm for feedforward categorization of objects and, in particular, human postures in real-time video sequences from address-event temporal-difference image sensors. The system employs an innovative ...
Ponencia
Focal-Plane Scale Space Generation with a 6T Pixel Architecture
(Society for Imaging Science and Technology, 2016)
Aiming at designing a CMOS image sensor that combines high fill factor and focal-plane implementation of instrumental image processing steps, we propose a simple modification in a standard pixel architecture in order ...
Artículo
A new high-level synthesis methodology of cascaded continuous-time ΣΔ modulators
(Institute of Electrical and Electronics Engineers, 2006)
This brief presents an efficient method for synthesizing cascaded sigma–delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time ...