ListarInstituto de Microelectrónica de Sevilla (IMSE-CNM) por materia "Layout-Aware Synthesis"
Mostrando ítems 1-2 de 2
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Ponencia
Geometrically-constrained, parasitic-aware synthesis of analog ICs
(The International Society for Optical Engineering - SPIE, 2005)In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as ...
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Ponencia
On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis
(The International Society for Optical Engineering - SPIE, 2005)Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between ...