Listar Instituto de Microelectrónica de Sevilla (IMSE-CNM) por autor "Domínguez Castro, Rafael"
Mostrando ítems 21-40 de 58
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Ponencia
Analog neural networks for real-time constrained optimization
(Institute of Electrical and Electronics Engineers, 1990)Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI ...
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Artículo
Analog Neural Programmable Optimizers in CMOS VLSI Technologies
(Institute of Electrical and Electronics Engineers, 1992)A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial ...
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Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template ...
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Ponencia
Architectures and building blocks for CMOS VLSI analog "neural" programmable optimizers
(Institute of Electrical and Electronics Engineers, 1992)A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization ...
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Ponencia
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
(Institute of Electrical and Electronics Engineers, 2002)A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the ...
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Ponencia
Challenges in mixed-signal IC design of CNN chips in submicron CMOS
(Institute of Electrical and Electronics Engineers, 1998)Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision ...
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Ponencia
CMOS Architectures and circuits for high-speed decision-making from image flows
(The International Society for Optical Engineering (SPIE), 2008)We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by ...
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CMOS optical-sensor array with high output current levels and automatic signal-range centring
(Institution of Engineering and Technology, 1994)A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range ...
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Ponencia
CMOS realization of a 2-layer CNN universal machine chip
(Institute of Electrical and Electronics Engineers, 2002)Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically ...
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Ponencia
CNN universal chip in CMOS technology
(Institute of Electrical and Electronics Engineers, 1994)This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of ...
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Ponencia
Convergence and stability of the FSR CNN model
(Institute of Electrical and Electronics Engineers, 1994)Stability and convergency results are reported for a modified continuous-time CNN model. The signal range of the state ...
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Artículo
Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
(Institute of Electrical and Electronics Engineers, 1993)This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) ...
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Ponencia
Design considerations for a low-noise CMOS image sensor
(SPIE- The International Society for Optical Engineering, 2015)This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced ...
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Ponencia
Design of a programmable mixed-signal CMOS image-processing chip in 0.8 /spl mu/m CMOS
(Institute of Electrical and Electronics Engineers, 1997)An operational vision-chip prototype with a wide-range of potential applications in artificial-vision systems is presented. ...
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Ponencia
Experimental demonstration of real-time image-processing using a VLSI analog programmable array processor
(SPIE- The International Society for Optical Engineering, 2000)This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitallyprogrammable analog ...
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Ponencia
Four-quadrant one-transistor-synapse for high-density CNN implementations
(Institute of Electrical and Electronics Engineers, 1998)Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation ...
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Artículo
Global design of analog cells using statistical optimization techniques
(Springer, 1994)We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. ...
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Ponencia
High-speed global shutter CMOS machine vision sensor with high dynamic range image acquisition and embedded intelligence
(The International Society for Optics and Photonics, 2012)High-speed imagers are required for industrial applications, traffic monitoring, robotics and unmanned vehicles, moviemaking, ...
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Ponencia
Hybrid-control of synapse circuits for programmable cellular neural networks
(Institute of Electrical and Electronics Engineers, 1996)This paper describes a hybrid weight-control strategy for VLSI realizations of programmable Cellular Neural Networks (CNNs), ...
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Ponencia
Implementation of non-linear templates using a decomposition technique by a 0.5 /spl mu/m CMOS CNN universal chip
(Institute of Electrical and Electronics Engineers, 2000)This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new ...