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Mostrando ítems 11-18 de 18
Ponencia
A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibration
(Institute of Electrical and Electronics Engineers, 2014)
his paper reports an integrated 64-channel neural recording sensor. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration mechanism which ...
Ponencia
A FPP-oriented tone mapping technique for high dynamic range imagers using temporal and final exposure measurements
(Institute of Electrical and Electronics Engineers, 2010)
This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors due to its very limited computing requirements since only local memories and a comparator ...
Ponencia
A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors
(Institute of Electrical and Electronics Engineers, 2012)
This paper introduces a two-tier CMOS-3D architecture for generation of Gaussian pyramids, detection of extrema, and calculation of spatial derivatives in an image. Such tasks are included in modern feature detectors, which ...
Ponencia
A behavioral modeling concept and practice of CNN-UM VLSI implementations
(Institute of Electrical and Electronics Engineers, 2001)
In this paper we introduce a novel simulation time bounded behavioral modeling technique that optimally selects the incorporated block models. The method has been specially developed for fast performance evaluation of large ...
Ponencia
High-order cascade multi-bit Σ∆ modulators for high-speed A/D conversion
(Universidad Carlos III, 1998)
The use of Sigma-Delta (Σ∆) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at ...
Ponencia
A hierarchical approach for the symbolic analysis of large analog integrated circuits
(IEEE computer society digital library, 2000)
This paper introduces a new hierarchical analysis methodology which incorporates approximation strategies during the analysis process. Consequently, the circuit sizes that can be analyzed increase dramatically, ...
Ponencia
Live Demonstration: Low-Power Low-CostCyber-Physical System for Bird Monitoring
(IEEE, 2018)
This live demonstration showcases a cyber-physical system tailored for inexpensive remote bird monitoring. A comprehensive analysis of the application requirements along with a tight system integration have given rise to ...
Ponencia
VersaTile Convolutional Neural Network Mapping on FPGAs
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Convolutional Neural Networks (ConvNets) are directed acyclic graphs with node transitions determined by a 1 set of configuration parameters. In this paper, we describe a 2 dynamically configurable hardware architecture ...