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Mostrando ítems 31-40 de 145
Ponencia
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Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)
Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, ...
Ponencia
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Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
(Institute of Electrical and Electronics Engineers, 2002)
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images ...
Ponencia
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On-The-Fly Deployment of Deep Neural Networks on Heterogeneous Hardware in a Low-Cost Smart Camera
(Association for Computing Machinery, 2018)
This demo showcases a low-cost smart camera where different hardware configurations can be selected to perform image recognition on deep neural networks. Both the hardware configuration and the network model can be changed ...
Ponencia
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Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor
(Institute of Electrical and Electronics Engineers, 2011)
This paper presents Wi-FLIP, a vision-enabled WSN node resulting from the integration of FLIP-Q, a prototype vision chip, and Imotel, a commercial WSN platform. In Wi-FLIP, image processing is not only constrained to the ...
Artículo
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SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of ...
Ponencia
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3D multi-layer vision architecture for surveillance and reconnaissance applications
(Institute of Electrical and Electronics Engineers, 2009)
The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is ...
Artículo
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Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors
(Institute of Electrical and Electronics Engineers, 2017)
Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple ...
Capítulo de Libro
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VISCUBE: A multi-layer vision chip
(Springer Science+Business Media, 2011)
Vertically integrated focal-plane sensor-processor chip design, combining image sensor with mixed-signal and digital processor arrays on a four layer structure is introduced. The mixed-signal processor array is designed ...
Artículo
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Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
(Institute of Electrical and Electronics Engineers, 2004)
Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual ...
Artículo
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A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision
(Institute of Electrical and Electronics Engineers, 2003)
A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics ...