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Mostrando ítems 21-30 de 145
Ponencia
In-pixel Voltage-Controlled Ring-Oscillator for Phase Interpolation in ToF Image Sensors
(2016)
The design and measurements of a CMOS pseudodifferential voltage-controlled ring-oscillator (VCRO) are presented. It is aimed to act as time interpolator for arrayable picosecond time-to-digital convertors (TDC). This ...
Ponencia
An ultra-low-power voltage-mode asynchronous WTA-LTA circuit
(Institute of Electrical and Electronics Engineers, 2013)
This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimummaximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. ...
Ponencia
Design of a compact and low-power TDC for an array of SiPM's in 110nm CIS technology
(Institute of Electrical and Electronics Engineers, 2017)
Silicon photomultipliers (SiPMs) are meant to substitute photomultiplier tubes in high-energy physics detectors and nuclear medicine. This is because of their -to name a few interesting properties- compactness, lower bias ...
Artículo
Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction
(Institute of Electrical and Electronics Engineers, 2017)
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale invariance, which permits having ...
Ponencia
Color Tone-Mapping Circuit for a Focal-Plane Implementation
(IEEE, 2018)
In this article, we present a review of the driving principles and parameters of a previously reported focal-plane tone-mapping operator. We then extend it in order to include color information processing. The signal ...
Ponencia
On the design of a sparsifying dictionary for compressive image feature extraction
(Institute of Electrical and Electronics Engineers, 2015)
Compressive sensing is an alternative to Nyquist-rate sampling when the signal to be acquired is known to be sparse or compressible. A sparse signal has a small number of nonzero components compared to its total length. ...
Artículo
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)
This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple ...
Ponencia
Real-time single-exposure ROI-driven HDR adaptation based on focal-plane reconfiguration
(Society of Photo-Optical Instrumentation Engineers, 2015)
This paper describes a prototype smart imager capable of adjusting the photo-integration time of multiple regions of interest concurrently, automatically and asynchronously with a single exposure period. The operation is ...
Ponencia
A CNN-driven locally adaptive CMOS image sensor
(Institute of Electrical and Electronics Engineers, 2004)
A bioinspired model for mixed-signal array mimics the way in which images are processed in the visual pathway. Focal-plane processing of images permits local adaptation of photoreceptor structures in silicon. Beyond simple ...
Ponencia
Mixed-signal CNN array chips for image processing
(The International Society for Optical Engineering, 1996)
Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, ...