Buscar
Mostrando ítems 41-50 de 50
Ponencia
Design of an analog/digital truly random number generator
(Institute of Electrical and Electronics Engineers, 1990)
An analog-digital system is presented for the generation of truly random (aperiodic) digital sequences. This model is based on a very simple piecewise-linear discrete map which is suitable for implementation using monolithic ...
Artículo
Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light ...
Ponencia
A Model for VLSI implementation of CNN image processing chips using current-mode techniques
(Institute of Electrical and Electronics Engineers, 1993)
A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. Current-mode building blocks are presented for the design of CMOS image preprocessing chips (feature ...
Ponencia
A novel CMOS analog neural oscillator cell
(Institute of Electrical and Electronics Engineers, 1989)
A very flexible programmable CMOS analog neural oscillator cell architecture is presented. The proposed neuron circuit architecture is a hysteretic neural-type pulse oscillator. Its implementation consists of a transconductance ...
Ponencia
Very high frequency CMOS OTA-C quadrature oscillators
(Institute of Electrical and Electronics Engineers, 1990)
An approach to the design of high-frequency monolithic voltage-controlled oscillators using operational transconductance amplifiers and capacitors is given. Results from two 3 μm CMOS prototypes are presented. Both frequency ...
Ponencia
Some design trade-offs for large CNN chips using small-size transistors
(Institute of Electrical and Electronics Engineers, 1997)
Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular Neural Network (CNN) chips. The inverse dependency of mismatch with transistor sizes may result in ...
Ponencia
Tool for fast mismatch analysis of analog circuits
(Institute of Electrical and Electronics Engineers, 1995)
A tool is presented that evaluates statistical deviations in performance characteristics of analog circuits, starting from statistical deviations in the technological parameters of MOS transistors. Performance is demonstrated ...
Artículo
High-Frequency Design of the Wien-Bridge Oscillator Using Composite Amplifiers
(Institute of Electrical and Electronics Engineers, 1987)
Artículo
A CMOS analog adaptive BAM with on-chip learning and weight refreshing
(Institute of Electrical and Electronics Engineers, 1993)
In this paper we will extend the transconductance-mode (T-mode) approach [1] to implement analog continuous-time neural network hardware systems to include on-chip Hebbian learning and on-chip analog weight storage capability. ...
Ponencia
A CMOS Implementation of Fitzhugh-Nagumo Neuron Model
(Institute of Electrical and Electronics Engineers, 1990)
A CMOS circuit is proposed that emulates FitzHugh-Nagumo's differential equations using OTAs, diode connected MOSFETs and capacitors. These equations model the fundamental behavior of biological neuron cells. Fitz- ...