Buscar
Mostrando ítems 401-410 de 428
Ponencia
A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing
(Institute of Electrical and Electronics Engineers, 1998)
An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor ...
Artículo
Algorithm for efficient symbolic analysis of large analogue circuits
(Institution of Engineering and Technology, 1994)
An algorithm is presented that generates simplified symbolic expressions for the small-signal characteristics of large analogue circuits. The expressions are approximated while they are computed, so that only the most ...
Tesis Doctoral
On The Design of Compressed Sensing CMOS Imagers
(2021-07-23)
El muestreo compresivo (CS) es una teoría de muestreo y una alternativa al proceso de muestreo basado en el teorema de Nyquist-Shannon. Mientras que el muestreo convencional aplica la fórmula de interpolación de Whittaker-Shannon ...
Artículo
High-Frequency Design of the Wien-Bridge Oscillator Using Composite Amplifiers
(Institute of Electrical and Electronics Engineers, 1987)
Patente
Fotomultiplicador digital de combinación or de pulsos
(Oficina Española de Patentes y Marcas , 2022-01-21)
Fotomultiplicador digital de combinación OR de pulsos.El fotomultiplicador comprende un conjunto de macroceldas, cada una de ellas comprendiendo al menos dos microceldas (1), estando cada una conectada a un nudo de salida ...
Ponencia
ACE16K: A 128×128 focal plane analog processor with digital I/O
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The ...
Ponencia
Simplified state update calculation for fast and accurate digital emulation of CNN dynamics
(Institute of Electrical and Electronics Engineers, 2010)
Compared to other one-step integration methods, the 4th-order Runge-Kutta is much more accurate while still consisting in a rather reduced algorithmic structure. However, in terms of the computing power, it is more expensive ...
Artículo
Offset-calibration with Time-Domain Comparators Using Inversion-mode Varactors
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective ...
Artículo
A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement
(SPIE, 2015)
The design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and ...
Ponencia
A hierarchical approach for the symbolic analysis of large analog integrated circuits
(IEEE computer society digital library, 2000)
This paper introduces a new hierarchical analysis methodology which incorporates approximation strategies during the analysis process. Consequently, the circuit sizes that can be analyzed increase dramatically, ...