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Ponencia
On neuromorphic spiking architectures for asynchronous STDP memristive systems
(IEEE Computer Society, 2010)
Neuromorphic circuits and systems techniques have great potential for exploiting novel nanotechnology devices, which suffer from great parametric spread and high defect rate. In this paper we explore some potential ways ...
Artículo
An Instant-Startup Jitter-Tolerant Manchester- Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links
(IEEE Computer Society, 2011)
This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage ...
Ponencia
High-Speed Serial Interfaces for Event-Driven Neuromorphic Systems
(IEEE Computer Society, 2015)
Neuromorphic Engineering is the discipline of building sensory processing artificial systems inspired in the neural processing found in living beings. Biological neural brains show massive connectivity among neurons, ...
Ponencia
A spatial calibrated AER contrast retina with adjustable contrast threshold
(2009)
Address Event Representation (AER) is an emergent technology for assembling modular multi-blocks bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since ...
Ponencia
An AER Contrast Retina with On-Chip Calibration
(IEEE Computer Society, 2007)
We present a contrast retina microchip that provides its output as an AER (Address Event Representation) stream. Contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels ...
Artículo
A calibration technique for very low current and compact tunable neuromorphic cells: Application to 5-bit 20nA DACs
(Institute of Electrical and Electronics Engineers, 2008)
Low current applications, like neuromorphic circuits, where operating currents can be as low as a few nanoamperes or less, suffer from huge transistor mismatches, resulting in around or less than 1-bit precisions. Recently, ...
Ponencia
A Precise CMOS Mismatch Model for Analog Design from Weak to Strong Inversion
(IEEE Computer Society, 2004)
A five parameter mismatch model continuos from weak to strong inversion is presented. The model is an extension of a previously reported one valid in the strong inversion region [1]. A mismatch characterization of NMOS ...
Ponencia
A signed spatial contrast event spike retina chip
(IEEE Computer Society, 2010)
Reported AER (Address Event Representation) contrast retinae perform a contrast computation based on the ratio between a pixel's local light intensity and a spatially weighted average of its neighbourhood. This results in ...
Ponencia
Design of adaptive nano/CMOS neural architectures
(IEEE Computer Society, 2012)
Memristive devices are a promising technology to implement dense learning synapse arrays emulating the high memory capacity and connectivity of biological brains. Recently, the implementation of STDP learning in memristive ...