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Mostrando ítems 1-10 de 11
Ponencia
Digital processor array implementation aspects of a 3D multi-layer vision architecture
(Institute of Electrical and Electronics Engineers, 2010)
Technological aspects of the 3D integration of a multilayer combined mixed-signal and digital sensor-processor array chip is described. The 3D integration raises the question of signal routing, power distribution, and heat ...
Artículo
A 3-D Chip Architecture for Optical Sensing and Concurrent Processing
(SPIE, 2010)
This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information ...
Ponencia
Transformer based front-end for a low power 2.4 GHz transceiver
(Institute of Electrical and Electronics Engineers, 2010)
A low power transceiver architecture for the 2.4 GHz ISM band using a 1.0 V supply is presented. It employs a transformer to convert the 100 Ω antenna impedance to almost 1 kΩ and so facilitates a low power transmitter and ...
Ponencia
On-site forest fire smoke detection by low-power autonomous vision sensor
(2010)
Early detection plays a crucial role to prevent forest fires from spreading. Wireless vision sensor networks deployed throughout high-risk areas can perform fine-grained surveillance and thereby very early detection and ...
Ponencia
A CMOS vision system on-chip with multicore sensory processing ar- chitecture for image analysis above 1,000F/s
(Spie, 2010)
This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip embedded structures, and generation of pertinent reaction commands at thousand’s frame-per-second ...
Ponencia
Baseband-processor for a passive UHF RFID transponder
(Institute of Electrical and Electronics Engineers, 2010)
This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID transponders, and proposes different techniques for reducing its power consumption. The processor has been ...
Ponencia
Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture ...
Ponencia
A FPP-oriented tone mapping technique for high dynamic range imagers using temporal and final exposure measurements
(Institute of Electrical and Electronics Engineers, 2010)
This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors due to its very limited computing requirements since only local memories and a comparator ...
Ponencia
In-pixel ADC for a vision architecture on CMOS-3D technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne surveillance and reconnaissance applications. The 3D chip architecture comprises a sensor layer with a ...
Ponencia
A prototype node for wireless vision sensor network applications development
(Institute of Electrical and Electronics Engineers, 2010)
This paper presents a prototype vision-enabled sensor node based on a commercial vision system of reduced size and power consumption. The wireless infrastructure for the deployment of a distributed smart camera network ...