dc.creator | Jiménez Fernández, Carlos Jesús | es |
dc.creator | Baena Oliva, María del Carmen | es |
dc.creator | Parra Fernández, María del Pilar | es |
dc.creator | Potestad Ordóñez, Francisco Eugenio | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.date.accessioned | 2021-03-12T12:25:09Z | |
dc.date.available | 2021-03-12T12:25:09Z | |
dc.date.issued | 2020 | |
dc.identifier.citation | Jiménez Fernández, C.J., Baena Oliva, M.d.C., Parra Fernández, M.d.P., Potestad Ordóñez, F.E. y Valencia Barrero, M. (2020). An Academic Approach to FPGA Design Based on a Distance Meter Circuit. IEEE Revista Iberoamericana de Tecnologias del Aprendizaje, 15 (3), 123-128. | |
dc.identifier.issn | 1932-8540 | es |
dc.identifier.uri | https://hdl.handle.net/11441/106006 | |
dc.description.abstract | Digital design learning at Register Transfer (RT)
level requires practical and complex examples as learning
progresses. FPGAs and development boards offer a suitable
platform for the implementation of these designs. However,
classroom practice sessions usually last two hours, which does
not allow the complexity of the designs be high enough. For
this reason, interesting designs that can be made in several
sessions are required. In this paper, the construction of a distance
measuring system is presented. For this purpose, a distance
measurement module based on ultrasound is available, the results
are displayed in 7-segment displays on a Nexys4 board. This
approach has been applied to three Electronic subjects at the
University of Seville. The degree of satisfaction on the part of the
students as well as the result of the evaluation of the experience
by the teachers involved are shown. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2013-45523-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2016-80549-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad CSIC 201550E039 | es |
dc.format | application/pdf | es |
dc.format.extent | 6 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | IEEE Revista Iberoamericana de Tecnologias del Aprendizaje, 15 (3), 123-128. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Active learning methodologies | es |
dc.subject | Project based learning (PBL) | es |
dc.subject | VHDL | es |
dc.subject | Digital systems design | es |
dc.subject | Distance meter | es |
dc.subject | Field programmable gate arrays (FPGA) | es |
dc.title | An Academic Approach to FPGA Design Based on a Distance Meter Circuit | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC2013-45523-R | es |
dc.relation.projectID | TEC2016-80549-R | es |
dc.relation.projectID | CSIC 201550E039 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/abstract/document/9137385 | es |
dc.identifier.doi | 10.1109/RITA.2020.3008343 | es |
dc.journaltitle | IEEE Revista Iberoamericana de Tecnologias del Aprendizaje | es |
dc.publication.volumen | 15 | es |
dc.publication.issue | 3 | es |
dc.publication.initialPage | 123 | es |
dc.publication.endPage | 128 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |