dc.creator | Potestad Ordóñez, Francisco Eugenio | es |
dc.creator | Jiménez Fernández, Carlos Jesús | es |
dc.creator | Valencia Barrero, Manuel | es |
dc.date.accessioned | 2021-03-10T06:53:25Z | |
dc.date.available | 2021-03-10T06:53:25Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | Potestad Ordóñez, F.E., Jiménez Fernández, C.J. y Valencia Barrero, M. (2016). Experimental and Timing Analysis Comparison of FPGA Trivium Implementations and their Vulnerability to Clock Fault Injection. En DCIS 2016: Conference on Design of Circuits and Integrated Systems Granada, España: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-5090-4565-5 | es |
dc.identifier.uri | https://hdl.handle.net/11441/105826 | |
dc.description.abstract | The security of cryptocircuits is today threatened
not only by attacks on algorithms but also, and above all, by
attacks on the circuit implementations themselves. These are
known as side channel attacks. One variety is the Active Fault
Analysis attack, that can make a circuit vulnerable by changing
its behavior in a certain way. This article presents an experimental
fault insertion attack on an FPGA implementation of the Trivium
stream cipher. It also compares the faults introduced with the
faults expected after a timing analysis. The results show that this
implementation is vulnerable to such attacks, and also that it
is not possible to estimate the position of the inserted faults by
means of timing analysis. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2010-16870 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2013-45523-R | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad CSIC 201550E039 | es |
dc.format | application/pdf | es |
dc.format.extent | 6 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | DCIS 2016: Conference on Design of Circuits and Integrated Systems (2016). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Fault Attack | es |
dc.subject | Stream Cipher | es |
dc.subject | Trivium | es |
dc.subject | FPGA implementation | es |
dc.title | Experimental and Timing Analysis Comparison of FPGA Trivium Implementations and their Vulnerability to Clock Fault Injection | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC2010-16870 | es |
dc.relation.projectID | TEC2013-45523-R | es |
dc.relation.projectID | CSIC 201550E039 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/7845270 | es |
dc.identifier.doi | 10.1109/DCIS.2016.7845270 | es |
dc.eventtitle | DCIS 2016: Conference on Design of Circuits and Integrated Systems | es |
dc.eventinstitution | Granada, España | es |
dc.relation.publicationplace | New York, USA | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |