dc.creator | Tapiador Morales, Ricardo | es |
dc.creator | Maro, Jean-Matthieu | es |
dc.creator | Jiménez Fernández, Ángel Francisco | es |
dc.creator | Jiménez Moreno, Gabriel | es |
dc.creator | Benosman, Ryad B. | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.date.accessioned | 2021-02-12T07:57:07Z | |
dc.date.available | 2021-02-12T07:57:07Z | |
dc.date.issued | 2020-06 | |
dc.identifier.citation | Tapiador Morales, R., Maro, J., Jiménez Fernández, Á.F., Jiménez Moreno, G., Benosman, R.B. y Linares Barranco, A. (2020). Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA. Sensors, 20 (12), 3404-. | |
dc.identifier.issn | 1424-8220 | es |
dc.identifier.uri | https://hdl.handle.net/11441/104876 | |
dc.description.abstract | Neuromorphic vision sensors detect changes in luminosity taking inspiration from
mammalian retina and providing a stream of events with high temporal resolution, also known
as Dynamic Vision Sensors (DVS). This continuous stream of events can be used to extract
spatio-temporal patterns from a scene. A time-surface represents a spatio-temporal context for a
given spatial radius around an incoming event from a sensor at a specific time history. Time-surfaces
can be organized in a hierarchical way to extract features from input events using the Hierarchy Of
Time-Surfaces algorithm, hereinafter HOTS. HOTS can be organized in consecutive layers to extract
combination of features in a similar way as some deep-learning algorithms do. This work introduces
a novel FPGA architecture for accelerating HOTS network. This architecture is mainly based on
block-RAM memory and the non-restoring square root algorithm, requiring basic components and
enabling it for low-power low-latency embedded applications. The presented architecture has been
tested on a Zynq 7100 platform at 100 MHz. The results show that the latencies are in the range of 1
µs to 6.7 µs, requiring a maximum dynamic power consumption of 77 mW. This system was tested
with a gesture recognition dataset, obtaining an accuracy loss for 16-bit precision of only 1.2% with
respect to the original software HOTS. | es |
dc.description.sponsorship | Spanish government and the European Regional Development Fund COFNET TEC2016-77785-P | es |
dc.description.sponsorship | Spanish government and the European Regional Development Fund MIND-ROB PID2019-105556GB-C33 | es |
dc.format | application/pdf | es |
dc.format.extent | 16 p. | es |
dc.language.iso | eng | es |
dc.publisher | MDPI | es |
dc.relation.ispartof | Sensors, 20 (12), 3404-. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Dynamic vision sensors | es |
dc.subject | Event-based | es |
dc.subject | Synchronous digital VLSI | es |
dc.subject | HDL | es |
dc.subject | FPGA | es |
dc.subject | Pattern recognition | es |
dc.subject | AER | es |
dc.title | Event-Based Gesture Recognition through a Hierarchy of Time-Surfaces for FPGA | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | TEC2016-77785-P | es |
dc.relation.projectID | PID2019-105556GB-C33 | es |
dc.relation.publisherversion | https://www.mdpi.com/1424-8220/20/12/3404 | es |
dc.identifier.doi | 10.3390/s20123404 | es |
dc.contributor.group | Universidad de Sevilla. TEP108: Robótica y Tecnología de Computadores | es |
dc.journaltitle | Sensors | es |
dc.publication.volumen | 20 | es |
dc.publication.issue | 12 | es |
dc.publication.initialPage | 3404 | es |