dc.creator | Guerrero Martos, David | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Ostúa Arangüena, Enrique | es |
dc.creator | Viejo Cortés, Julián | es |
dc.date.accessioned | 2021-02-11T11:59:39Z | |
dc.date.available | 2021-02-11T11:59:39Z | |
dc.date.issued | 2007 | |
dc.identifier.citation | Guerrero Martos, D., Bellido Díaz, M.J., Juan Chico, J., Millán Calderón, A., Ruiz de Clavijo Vázquez, P., Ostúa Arangüena, E. y Viejo Cortés, J. (2007). Automatic logic synthesis for parallel alternating latches clocking schemes. En Microtechnologies for the New Millennium 2007 Maspalomas, Gran Canaria, España: SPIE Digital Library. | |
dc.identifier.issn | 0277-786X | es |
dc.identifier.uri | https://hdl.handle.net/11441/104860 | |
dc.description.abstract | This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so
called Parallel Alternating Latches Clocking Schemes (PALACS). The proposed method greatly improves the
applicability of PALACS and its benefits. This technique is verified through design examples in three different CMOS
processes and using logic level simulation, with successful results in all the cases. | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TEC-2004-00840-MIC | es |
dc.format | application/pdf | es |
dc.format.extent | 9 | es |
dc.language.iso | eng | es |
dc.publisher | SPIE Digital Library | es |
dc.relation.ispartof | Microtechnologies for the New Millennium 2007 (2007). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Clock skew tolerance | es |
dc.subject | High speed CMOS design | es |
dc.subject | CAD circuit design | es |
dc.title | Automatic logic synthesis for parallel alternating latches clocking schemes | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC-2004-00840-MIC | es |
dc.relation.publisherversion | https://www.spiedigitallibrary.org/conference-proceedings-of-spie/6590/659006/Automatic-logic-synthesis-for-parallel-alternating-latches-clocking-schemes/10.1117/12.723664.full | es |
dc.identifier.doi | 10.1117/12.723664 | es |
dc.contributor.group | Universidad de Sevilla. TIC204: Investigación y Desarrollo Digital | es |
dc.eventtitle | Microtechnologies for the New Millennium 2007 | es |
dc.eventinstitution | Maspalomas, Gran Canaria, España | es |
dc.relation.publicationplace | Bellingham, WA | es |
dc.contributor.funder | Ministerio de Educación y Ciencia (MEC). España | es |