dc.creator | Ostúa Arangüena, Enrique | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Viejo Cortés, Julián | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Guerrero Martos, David | es |
dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.date.accessioned | 2021-02-05T10:33:15Z | |
dc.date.available | 2021-02-05T10:33:15Z | |
dc.date.issued | 2006 | |
dc.identifier.citation | Ostúa Arangüena, E., Juan Chico, J., Viejo Cortés, J., Bellido Díaz, M.J., Guerrero Martos, D., Millán Calderón, A. y Ruiz de Clavijo Vázquez, P. (2006). A SoC Design Methodology for LEON2 on FPGA. En IWS 2006: XII Taller IBERCHIP San José, Costa Rica: IBERCHIP. | |
dc.identifier.uri | https://hdl.handle.net/11441/104648 | |
dc.description.abstract | SoC design methodologies show up as a natural and
productive method to implement embedded and/or
ubiquitous systems. The authors explore the
possibilities of the free LEON2 processor core,
originally developed by the European Space Agency,
and the Xilinx FPGA family to develop a complete
SoC design methodology for both hardware and
software. Advantages of the platform and productivity
of the proposed methodology are highlighted through
an application example, showing the suitability of
LEON2 implemented on FPGA for professional-grade
applications. | es |
dc.format | application/pdf | es |
dc.format.extent | 9 | es |
dc.language.iso | eng | es |
dc.publisher | IBERCHIP | es |
dc.relation.ispartof | IWS 2006: XII Taller IBERCHIP (2006). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | A SoC Design Methodology for LEON2 on FPGA | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.publisherversion | http://161.111.232.132/iberchip2006/ponencias.html | es |
dc.eventtitle | IWS 2006: XII Taller IBERCHIP | es |
dc.eventinstitution | San José, Costa Rica | es |
dc.relation.publicationplace | San José, Costa Rica | es |