Artículo
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
Autor/es | Núñez Martínez, Juan
Avedillo de Juan, María José |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2016 |
Fecha de depósito | 2018-04-12 |
Publicado en |
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Resumen | In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than ... In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España |
Identificador del proyecto | TEC2013-40670-P |
Cita | Nuñez Martínez, J. y Avedillo de Juan, M.J. (2016). Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas. IEEE Journal on Electron Devices, 63 (12), 5012-5020. |
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