Ponencias (Ingeniería Electrónica)

URI permanente para esta colecciónhttps://hdl.handle.net/11441/11359

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FSC-MPC Switching Phase Control for Interleaved DC/DC Vehicle Charger
(Institute of Electrical and Electronics Engineers, 2025-04) Aguirre, Matías; Vázquez Pérez, Sergio; León Galván, José Ignacio; García Franquelo, Leopoldo; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC109: Tecnología
Interleaved converter configurations are a common solution for the charging of electric vehicles. Carrier phase shift is a common and important design element for these converters. Recent research shows that a proper regulation of the phase shift can improve the system performance. This requires more complex controllers and actuation capabilities. Finite Control Set Model Predictive Control (FCS-MPC) has the capability to manage multiple control. Recent research has managed to achieve a satisfactory switching frequency control through a period control approach (PCA) for a single power converter. However, it does not control the switching phase required for an interleaved operation with parallel converters. This paper presents the design and implementation of a switching phase control for PCA-FCS-MPC, allowing the operation of an interleaved configuration. The performance is evaluated for different operating point through experimental validation.
Gain Scheduling PI Voltage Control of Three-phase AC/DC Power Converters
(Springer Nature, 2025-04) Rodríguez Rubio, Francisco; Vázquez Pérez, Sergio; Castaño Castaño, Luis Fernando; Carrasco Solís, Juan Manuel; Ortega Linares, Manuel Gil; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. Departamento de Ingeniería de Sistemas y Automática; Ministerio de Ciencia e Innovación (MICIN). España; Universidad de Sevilla. TIC109: Tecnología; Universidad de Sevilla. TEP201: Ingeniería de Automatización, Control y Robótica
This paper present a dc-Link voltage regulation strategy for a two-Level three-phase grid-connected power converter. Control objectives for this system are regulating the dc-link capacitor voltage to a user define set point and, tracking the grid current reference to inject or absorb the requested instantaneous active and reactive power. The proposed voltage controller has a PI Control structure, with adaptation of the gains depending on the observed error. In this way, the monitoring of the voltage reference can be intelligently optimized.
Feed-forward Technique to Emulate Natural Sampling Method for Cascaded H-bridge Converters
(Institute of Electrical and Electronics Engineers, 2023-11) Márquez Alcaide, Abraham; Vázquez Pérez, Sergio; Aguilera, Ricardo P.; Kouro, Samir; León Galván, José Ignacio; García Franquelo, Leopoldo; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Ciencia e Innovación (MICIN). España; Universidad de Sevilla. TIC109: Tecnología
Phase-shifted pulse width modulation (PS-PWM) is one of the preferred modulation strategies for cascaded H-bridge (CHB) converters due to its excellent harmonic performance. Nevertheless, this modulation strategy needs a fast sampling frequency, which can increase with the number of H-bridge sub-modules (SMs). Moreover, the advantages related to the harmonic content of the output voltages are usually lost for applications that require unbalanced operation conditions regarding SM power or voltage references, such as solar PV or battery energy storage systems. This work proposes a feed-forward compensation technique that reduces the sampling frequency to two times the carrier frequency while maintaining the good harmonic performance of the CHB output voltages. Simulation results are carried out to compare and demonstrate the superior performance of the proposed technique.
Experimental Analysis of K-Best Sphere Decoding Algorithm for LPH-FCS-MPC
(Institute of Electrical and Electronics Engineers, 2022-10) Zafra, Eduardo; Vázquez Pérez, Sergio; Márquez Alcaide, Abraham; García Franquelo, Leopoldo; Pérez, Emilia; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Ciencia e Innovación (MICIN). España; Junta de Andalucía; Ministerio de Ciencia, Innovación y Universidades (MICIU). España; Universidad de Sevilla. TIC109: Tecnología
Finite control set model predictive control (FCS-MPC) with long prediction horizon (LPH-FCS-MPC) is becoming a great option for the control of power conversion systems. In contrast to short prediction horizon FCS-MPC, extending the prediction horizon length renders important steady-state improvements as the harmonic distortion and/or the switching frequency can be considerably reduced, for a more efficient operation of the power converter. The main disadvantage is that practical application of these strategies is still limited due to computational costs. In this work, a recently proposed hardware K-best sphere decoding algorithm (K-best SDA) is further analyzed and verified through experiments in an uninterruptible power supply (UPS) system. The results indicate the efficiency of the algorithm, enabling longer prediction horizons and better control performance in comparison with the conventional SDA.
DC-Link Voltage Regulation of Grid-Connected Converters Using Linear Disturbance Observer
(Institute of Electrical and Electronics Engineers, 2022-12) Luo, Wensheng; Shi, Tingyu; Vázquez Pérez, Sergio; Wang, Zilin; Wu, Ligang; García Franquelo, Leopoldo; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Ciencia e Innovación (MICIN). España; Universidad de Sevilla. TIC109: Tecnología
In this paper, a disturbance observer based control strategy is proposed to regulate the dc-link voltage of three-phase two-level pulse-width-modulation active-front-end rectifiers. In the voltage regulation loop, a linear disturbance observer is designed to improve the system performance. The load connected to the dc-link capacitor is considered as an external disturbance and the observer is used to estimate its value. The estimated disturbance is compensated to the PI controller. Simulations are carried out to verify the effectiveness and advantage of the proposed control strategy. Three different loads have been provided to test the robustness of the control strategy. Simulation results show that the proposed control strategy improves the transient response of the dc-link voltage, meanwhile maintains the steady-state performance in term of the output current total harmonic distortion, and has strong robustness against the external load variation.
Grid-Connected Inverter Control Via Linear Parameter-Varying System Approach
(Institute of Electrical and Electronics Engineers, 2022-12) Luo, Wensheng; Li, Shuhao; Vázquez Pérez, Sergio; Du, Jinqian; Wu, Ligang; García Franquelo, Leopoldo; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Ciencia e Innovación (MICIN). España; Universidad de Sevilla. TIC109: Tecnología
his paper is concerned with the controller design for grid-connected inverter facing parameter variation and stochastic perturbation. Considering these two factors, a stochastically perturbed linear parameter varying (LPV) system for the inverter is formulated, upon which the stability analysis and controller synthesis have been conducted. Parameter dependent sufficient conditions have been obtained to guarantee the asymptotical and exponential mean square stability, with which the asymptotical and exponential controllers are designed respectively. A two-level three-phase inverter is used to verify the effectiveness of proposed theories. Simulation results show that both the controllers are effective under parameter variation and stochastic perturbation, and the exponential controller performs better than the asymptotical controller.
Stability-Oriented Prediction Horizons Design of Generalized Predictive Control for DC/DC Boost Converter
(Institute of Electrical and Electronics Engineers (IEEE), 2024-05) LI, Yuan; Sahoo, Subham; Vázquez Pérez, Sergio; Zhang, Yichao; Dragicevic, Tomislav; Blaabjerg, Frede; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC109: Tecnología
This paper introduces a novel approach in designing prediction horizons on a generalized predictive control for a DC/DC boost converter. This method involves constructing a closed-loop system model and assessing the impact of different prediction horizons on system stability. In contrast to conventional design approaches that often rely on empirical prediction horizon selection or incorporate non-linear observers, the proposed method establishes a rigorous boundary for the prediction horizon to ensure system stability. This approach facilitates the selection of an appropriate prediction horizon while avoiding excessively short horizons that can lead to instability and preventing the adoption of unnecessarily long horizons that would burden the controller with high computational demands. Finally, the accuracy of the design method has been confirmed through experimental testing. Moreover, it has been demonstrated that the prediction horizon determined by this method reduces the computational burden by 10\%-20\% compared to the empirically selected prediction horizon.
Experiencia de homologación y adaptación del proyecto docente de la asignatura circuitos electrónicos
(2008) Martínez Heredia, Juana María; Colodro Ruiz, Francisco; Universidad de Sevilla. Departamento de Ingeniería Electrónica
El objetivo de este trabajo es la adaptación progresiva del proyecto docente de la asignatura Circuitos Electrónicos al Espacio Europeo de Educación Superior. Se ha participado en primer lugar en la Convocatoria 2006/2007 de Homologación y Acreditación de Proyectos Docentes de la Universidad de Sevilla, elaborando una primera versión del proyecto. Tras obtener la homologación, y con esa experiencia, se ha elaborado la guía docente en créditos ECTS para el actual curso académico 2007/2008.
Elaboración de contenidos y tareas docentes en el entorno de la plataforma de enseñanza virtual webct para la asignatura Circuitos Electrónicos
(2008) Martínez Heredia, Juana María; Colodro Ruiz, Francisco; Universidad de Sevilla. Departamento de Ingeniería Electrónica
En el actual contexto en el que las Universidades españolas se ven inmersas, es necesario ir introduciendo elementos de innovación educativa en la tradicional clase presencial. Este documento describe la elaboración de contenidos y tareas docentes en la plataforma de enseñanza virtual de la Universidad de Sevilla para el proceso de enseñanza-aprendizaje de la asignatura Circuitos Electrónicos. Los resultados han sido satisfactorios y marcan el camino a seguir en los próximos años.
Class AB output stages for low voltage CMOS opamps with accurate quiescent current control by means of dynamic biasing
(LIRMM, Université Montpellier II, 2000) Torralba Silgado, Antonio Jesús; González Carvajal, Ramón; Ramírez Angulo, Jaime; Martínez Heredia, Juana María; Pérez Vega-Leal, Alfredo; Universidad de Sevilla. Departamento de Ingeniería Electrónica
Two new class AB output stages for CMOS opamps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Simulation results are provided that are in good agreement with expected values.
A four quadrant, 1.4V Supply, wide, swing, high frequency CMOS analogue multiplier with high current efficiency
(LIRMM, Université Montpellier II, 2000) Ramírez Angulo, Jaime; González Carvajal, Ramón; Martínez Heredia, Juana María; Universidad de Sevilla. Departamento de Ingeniería Electrónica
A four quadrant analogue multiplier that operates with a 1.4V single supply and 0.6V peak-peak input signals on both inputs is presented. It is based on a new low-voltage class AB differential amplifier with quiescent current control Current Efficiency and Random Distortion are introduced as quality factors to evaluate the performance of the analog multiplier. The multiplier presented here is characterized by a high current efficiency (50%), high bandwidth (40MHz) and a high linearity (4% distortion). Experimental results of a test chip are shown that verify low-voltage, low distortion and wide swing operation. Post +layout simulations are presented that verify its wide bandwidth characteristics.
A 1.5V linear transconductor with wide bandwidth and wide input and output signal swings [DCIS 2000]
(LIRMM, Université Montpellier II, 2000) Ramírez Angulo, Jaime; González Carvajal, Ramón; Torralba Silgado, Antonio Jesús; Martínez Heredia, Juana María; Universidad de Sevilla. Departamento de Ingeniería Electrónica
A linear voltage-to-current converter that operates with a single supply voltage close to a transistor's threshold voltage and that has almost rail-rail input and output swings is introduced. The circuit is conceived as an input interface for current-mode signal processing systems. It also has applications for the implementation of other very low-voltage circuits like instrumentation amplifiers and common mode feedback control circuits. Simulations and experimental results of a test chip prototype in 1.2pm CMOS technology are presented that verify functionality of the proposed circuit and its broadband characteristics.
Analog Squaring Circuit based on Time Encoding
(2009) Colodro Ruiz, Francisco; Torralba Silgado, Antonio Jesús; Mora Jiménez, José Luis; Martínez Heredia, Juana María; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Ciencia Y Tecnología (MCYT). España
Accurate analog squarers are required for different signal processing functions, like amplitude modulation, frequency shifting, signal power estimation, and neural and image processing. Transistor-level analog squarers suffer from limited accuracy, especially in modern deep submicron technology where the squared law of the MOS transistor in the saturation region is no longer valid. Based on the Asynchronous Sigma-Delta Modulator (ASDM), a new circuit which provides the squared value of the input signal is proposed. In this paper, the proposed analog squarer is studied, and the analytical results are validated by simulation in the time domain. The effect of analog imperfections on the accuracy of the squarer is also analyzed showing that a high Signal to Noise plus Distortion Ratio can be obtained for typical values of the mismatch and up to frequencies near half the maximum frequency of the ASDM limit cycle.
Programmable ASICs for model predictive control
(Institute of Electrical and Electronics Engineers, 2015-06-18) Martínez Rodríguez, Macarena Cristina; Brox Jiménez, Piedad; Tena Sánchez, Erica; Acosta Jiménez, Antonio José; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Universidad de Sevilla. Departamento de Tecnología Electrónica; Ministerio de Economía y Competitividad (MINECO). España; Consejo Superior de Investigaciones Científicas (CSIC)
Two configurable and programmable ASICs that implement piecewise-affine (PWA) functions have been designed in TSMC 90-nm technology in response to industry demands for embedded, fast response time, and low power solutions for Model Predictive Control (MPC). An automated model-based design flow can extract the parameters necessary for the configuration and the programming of both ASICs. Two application examples in the automotive field illustrate the design flow and the behavior of the ASICs.
GreeAODV: An Energy Efficient Routing Protocol for Vehicular Ad Hoc Networks
(Springer Nature, 2018-07-06) Baker, Thar; García-Campos, José Manuel; Gutiérrez Reina, Daniel; Toral, S. L.; Tawfik, Hissam; Al-Jumeily, Dhiya; Hussain, Abir; Universidad de Sevilla. Departamento de Ingeniería Telemática; Universidad de Sevilla. Departamento de Ingeniería Electrónica
VANETs allow communications among vehicles, and vehicles with the roadside infrastructure, namely Vehicle-to-Vehicle (V2V) and Vehicle-to-Infrastructure (V2I) respectively, in smart cities. Due to the number of vehicles, the infrastructure elements, the size of scenarios and mobility of nodes, the energy consumed to discover routes between source and destination nodes and to transmit applications packets can be high. In this paper, we propose a GreeDi based reactive routing protocol aimed at selecting the most efficient route in terms of energy consumption between two nodes in VANETs. The route selection is based on the power consumed by the intermediate nodes between the source and destination nodes. The proposed algorithm has been evaluated in city map-based VANET scenarios. The simulation results confirm that the proposed algorithm outperforms the original AODV in terms of power consumption. Furthermore, a computational Intelligence driven approach to address the challenge of energy efficient routing optimisation, is discussed.
Towards a 3D-Printed and Autonomous Culture Platform Integrated with Commercial Microelectrode Arrays
(IEEE, 2021-06-09) Urbano Gámez, Jesús David; Aracil Fernández, Carmen; Perdigones Sánchez, Francisco; Fontanilla Martín, José Antonio; Quero Reboul, José Manuel; Universidad de Sevilla. Departamento de Ingeniería Electrónica
Biologists and physicians need tools that may study the biological mechanisms involved in the degeneration of tissues to understand and slow down the effects of the diseases. In this way, systems able to maintain a culture in its appropriate conditions, even long term, and compatible with electro-stimulation and acquisition, open a wide field of applications. The proposed design is a low-cost portable system that accomplishes all these requirements. It is based on the integration of an MEA with electronic systems, and a culture platform, offering the possibility of electro-stimulation of a cell or tissue culture and studying its electrical activity.
Radiation environment emulation for VLSI designs: a low cost platform based on xilinx FPGA’s
(Institute of Electrical and Electronics Engineers (IEEE), 2007-06) Nápoles Luengo, Javier; Guzmán-Miranda, Hipólito; Aguirre Martínez, M.A.; Tombs, Jonathan Noel; Muñoz Chavero, Fernando; Baena Lecuyer, Vicente; Torralba Silgado, Antonio Jesús; García Franquelo, Leopoldo; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC192: Ingeniería Electrónica
As technology shrinks, critical industral applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as Single Event Effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT-UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-IT. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80K faults per hour in a system with 2 million test vectors
A compiler-based infrastructure for fault-tolerant co-design
(Association for Computing Machinery (ACM), 2010-06) Restrepo Calle, Felipe; Martínez-Álvarez, Antonio; Guzmán-Miranda, Hipólito; Palomo Pinto, Rogelio; Aguirre Echanove, Miguel Ángel; Cuenca Asensi, Sergio; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Educación y Ciencia (MEC). España; Universidad de Sevilla. TIC192: Ingeniería Electrónica
The protection of processor-based systems to mitigate the harmful effects of transient faults (hardening) is gaining importance as technology shrinks. Hybrid hardware/software hardening approaches are promising alternatives in the design of such fault tolerant systems. This paper presents a compiler-based infrastructure for facilitating the exploration of the design space between hardware-only and software-only fault tolerant techniques. The compiler design is based on a generic architecture that facilitates the implementation of software-based techniques, providing an uniform isolated-from-target hardening core. In this way, these methods can be implemented in an architecture independent way and can easily integrate new protection mechanisms to automatically produce hardened code. The infrastructure includes a simulator that provides information about memory and execution time overheads to aid the designer in the co-design decisions. The tool-chain is complemented by a hardware fault emulation tool that allows to measure the fault coverage of the different solutions running on the real system. A case study was implemented allowing to evaluate the flexibility of the infrastructure to fit the reliability requirements of the system within their memory and performance restrictions.
Prototipado rápido de sistemas empotrados tolerantes a radiación en FPGA
(Institute of Electrical and Electronics Engineers (IEEE), 2010-07) Restrepo Calle, Felipe; Martínez-Álvarez, Antonio; Palomo Pinto, Rogelio; Guzmán-Miranda, Hipólito; Aguirre Echanove, Miguel Ángel; Cuenca Asensi, Sergio; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Educación y Ciencia (MEC). España; Universidad de Sevilla. TIC192: Ingeniería Electrónica
La creciente capacidad de integración de las FPGA está convirtiendo estos dispositivos en la plataforma preferida para el prototipado rápido de sistemas digitales complejos. Por otro lado, a medida que la tecnología se reduce, cobra importancia la protección de los sistemas frente a los fallos transitorios inducidos por radiación (por ejemplo los Single Event Upsets). En este trabajo se presenta una nueva aproximación de prototipado rápido para el codiseño de sistemas empotrados robustos usando FPGA. Dicha aproximación está soportada por una plataforma de endurecimiento que permite combinar técnicas de tolerancia a fallos basadas en software con técnicas basadas en hardware, obteniendo diferentes configuraciones hardware/software con diferentes niveles de compromiso entre restricciones de diseño, fiabilidad y coste. Como caso de estudio, se han desarrollado varios sistemas empotrados tolerantes a radiación basados en una versión del microprocesador PicoBlaze independiente de tecnología.
FTUNSHADES2: A novel platform for early evaluation of robustness against SEE
(Institute of Electrical and Electronics Engineers (IEEE), 2011-09) Mogollón García, Juan Manuel; Guzmán-Miranda, Hipólito; Nápoles, J.; Barrientos, J.; Aguirre Martínez, M.A.; Universidad de Sevilla. Departamento de Ingeniería Electrónica; European Space Agency (ESA); Ministerio de Ciencia e Innovación; Universidad de Sevilla. TIC192: Ingeniería Electrónica
Large digital integrated circuits designed to solve space applications, have to be designed following standards that recommend to include hardening techniques against Single Event Phenomena caused by harsh radiation environments. It is specifically important in the case of modern deep-submicron technologies. Single Event Effects are phenomena related to the effects of radiation when ionizing particles hit the surface of semiconductors in certain critical areas, where the consequences are mainly data corruption or unexpected behavior with no permanent damage. Fault injection studies are a valuable methodology to evaluate the robustness of the circuit mainly in the early stages of the design. This paper introduces the second generation of the emulation-based fault injection platform FTUNSHADES supported by the European Space Agency, where new features have been included to fulfill with the demands of a growing community of users.

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