Ponencias (Ingeniería Electrónica)

URI permanente para esta colecciónhttps://hdl.handle.net/11441/11359

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Towards a 3D-Printed and Autonomous Culture Platform Integrated with Commercial Microelectrode Arrays
(IEEE, 2021-06-09) Urbano Gámez, Jesús David; Aracil Fernández, Carmen; Perdigones Sánchez, Francisco; Fontanilla Martín, José Antonio; Quero Reboul, José Manuel; Universidad de Sevilla. Departamento de Ingeniería Electrónica
Biologists and physicians need tools that may study the biological mechanisms involved in the degeneration of tissues to understand and slow down the effects of the diseases. In this way, systems able to maintain a culture in its appropriate conditions, even long term, and compatible with electro-stimulation and acquisition, open a wide field of applications. The proposed design is a low-cost portable system that accomplishes all these requirements. It is based on the integration of an MEA with electronic systems, and a culture platform, offering the possibility of electro-stimulation of a cell or tissue culture and studying its electrical activity.
Radiation environment emulation for VLSI designs: a low cost platform based on xilinx FPGA’s
(Institute of Electrical and Electronics Engineers (IEEE), 2007-06) Nápoles Luengo, Javier; Guzmán-Miranda, Hipólito; Aguirre Martínez, M.A.; Tombs, Jonathan Noel; Muñoz Chavero, Fernando; Baena Lecuyer, Vicente; Torralba Silgado, Antonio Jesús; García Franquelo, Leopoldo; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC192: Ingeniería Electrónica
As technology shrinks, critical industral applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as Single Event Effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT-UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-IT. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80K faults per hour in a system with 2 million test vectors
A compiler-based infrastructure for fault-tolerant co-design
(Association for Computing Machinery (ACM), 2010-06) Restrepo Calle, Felipe; Martínez-Álvarez, Antonio; Guzmán-Miranda, Hipólito; Palomo Pinto, Rogelio; Aguirre Echanove, Miguel Ángel; Cuenca Asensi, Sergio; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Educación y Ciencia (MEC). España; Universidad de Sevilla. TIC192: Ingeniería Electrónica
The protection of processor-based systems to mitigate the harmful effects of transient faults (hardening) is gaining importance as technology shrinks. Hybrid hardware/software hardening approaches are promising alternatives in the design of such fault tolerant systems. This paper presents a compiler-based infrastructure for facilitating the exploration of the design space between hardware-only and software-only fault tolerant techniques. The compiler design is based on a generic architecture that facilitates the implementation of software-based techniques, providing an uniform isolated-from-target hardening core. In this way, these methods can be implemented in an architecture independent way and can easily integrate new protection mechanisms to automatically produce hardened code. The infrastructure includes a simulator that provides information about memory and execution time overheads to aid the designer in the co-design decisions. The tool-chain is complemented by a hardware fault emulation tool that allows to measure the fault coverage of the different solutions running on the real system. A case study was implemented allowing to evaluate the flexibility of the infrastructure to fit the reliability requirements of the system within their memory and performance restrictions.
Prototipado rápido de sistemas empotrados tolerantes a radiación en FPGA
(Institute of Electrical and Electronics Engineers (IEEE), 2010-07) Restrepo Calle, Felipe; Martínez-Álvarez, Antonio; Palomo Pinto, Rogelio; Guzmán-Miranda, Hipólito; Aguirre Echanove, Miguel Ángel; Cuenca Asensi, Sergio; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Educación y Ciencia (MEC). España; Universidad de Sevilla. TIC192: Ingeniería Electrónica
La creciente capacidad de integración de las FPGA está convirtiendo estos dispositivos en la plataforma preferida para el prototipado rápido de sistemas digitales complejos. Por otro lado, a medida que la tecnología se reduce, cobra importancia la protección de los sistemas frente a los fallos transitorios inducidos por radiación (por ejemplo los Single Event Upsets). En este trabajo se presenta una nueva aproximación de prototipado rápido para el codiseño de sistemas empotrados robustos usando FPGA. Dicha aproximación está soportada por una plataforma de endurecimiento que permite combinar técnicas de tolerancia a fallos basadas en software con técnicas basadas en hardware, obteniendo diferentes configuraciones hardware/software con diferentes niveles de compromiso entre restricciones de diseño, fiabilidad y coste. Como caso de estudio, se han desarrollado varios sistemas empotrados tolerantes a radiación basados en una versión del microprocesador PicoBlaze independiente de tecnología.
FTUNSHADES2: A novel platform for early evaluation of robustness against SEE
(Institute of Electrical and Electronics Engineers (IEEE), 2011-09) Mogollón García, Juan Manuel; Guzmán-Miranda, Hipólito; Nápoles, J.; Barrientos, J.; Aguirre Martínez, M.A.; Universidad de Sevilla. Departamento de Ingeniería Electrónica; European Space Agency (ESA); Ministerio de Ciencia e Innovación; Universidad de Sevilla. TIC192: Ingeniería Electrónica
Large digital integrated circuits designed to solve space applications, have to be designed following standards that recommend to include hardening techniques against Single Event Phenomena caused by harsh radiation environments. It is specifically important in the case of modern deep-submicron technologies. Single Event Effects are phenomena related to the effects of radiation when ionizing particles hit the surface of semiconductors in certain critical areas, where the consequences are mainly data corruption or unexpected behavior with no permanent damage. Fault injection studies are a valuable methodology to evaluate the robustness of the circuit mainly in the early stages of the design. This paper introduces the second generation of the emulation-based fault injection platform FTUNSHADES supported by the European Space Agency, where new features have been included to fulfill with the demands of a growing community of users.
Pareto Analysis of PI Tuning in Direct Digital Control of Multi-phase Drives
(Elsevier, 2024) Garrido Satué, Manuel; Álvarez, J.D.; Perales Esteve, Manuel Ángel; Universidad de Sevilla. Departamento de Ingeniería de Sistemas y Automática; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Ciencia e Innovación (MICIN). España; Agencia Estatal de Investigación. España; European Union (UE); European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER); Universidad de Sevilla. TEP201: Ingeniería de Automatización, Control y Robótica; Universidad de Sevilla. TEP203: Física Interdisciplinar Fundamentos y Aplicaciones
PI tuning for variable-speed multi-phase drives is a complex task. In this paper, a Pareto analysis is introduced to reveal not previously reported links between figures of merit. The drive used for the study includes a 5-phase induction motor supplied by a voltage source inverter. A finite state predictive method is used for the inner loop (current control). The outer loop (speed control) is governed by a PI. The analysis is done experimentally thus including all sorts of non-idealities not appearing in commonly found models. The experimental results show how the pursuit for better performance is hindered by the existence of links between figures of merit. The importance of the result lies in showing that arbitrary performance enhancements are not possible in a general case.
Two complementary approaches for studying the effects of SEUs on HDL-based designs
(Institute of Electrical and Electronics Engineers (IEEE), 2014-08) Mansour, W.; Aguirre Echanove, Miguel Ángel; Guzmán-Miranda, Hipólito; Barrientos, J.; Velazco, R.; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC192: Ingeniería Electrónica
In this paper, a comparison between two HDL-based fault-injection methods, FT-UNSHADES and NETFI, is presented. Fault-injection campaigns were performed on a third party example, named KECCAK sponge function family circuit dedicated for cryptography which is available as an open core. The comparison of both methodologies shows a similarity in the results and enlightens a problem that affects fault-injection systems related to how the synthesis and the simulation is made.
FPGA-based mimicking of cryptographic device hacking through fault injection attacks
(Institute of Electrical and Electronics Engineers (IEEE), 2015-06) Martín-Valencia, José Manuel; Guzmán-Miranda, Hipólito; Aguirre Echanove, Miguel Ángel; Universidad de Sevilla. Departamento de Ingeniería Electrónica; European Union; Universidad de Sevilla. TIC192: Ingeniería Electrónica
Cryptographic algorithms are at the core of secure communications applications. To improve computation speed and power consumption, it is common for these algorithms to be implemented into application-specific hardware processors, for example in Smart Cards. As with any other digital circuit, the internal memory elements, such as flip-flops, of these digital implementations can flip their value when the silicon is subjected to ionizing radiation or a high-energy light source. Hackers exploit this behavior by using laser light to perform what are commonly called fault attacks. After injecting the fault, the attacker records the faulty output pattern and performs specific post-processing operations which allow him to determine some bits of the internal encryption key. Repeating this process for different plaintexts, a malicious actor can obtain the complete encryption key, or enough bits that a brute-force attack over the remaining bits becomes feasible. The present paper explores how to reproduce fault injection attacks on a cryptographic core implemented physically in an FPGA. Reproducing the fault attacks in the FPGA implementation will allow engineers to better study and implement mitigations and protections against these kinds of attacks in future designs
Selective Protection Analysis Using a SEU Emulator: Testing Protocol and Case Study Over the Leon2 Processor
(Institute of Electrical and Electronics Engineers (IEEE), 2007-08) Aguirre Martínez, M.A.; Tombs, Jonathan Noel; Muñoz Chavero, Fernando; Baena Lecuyer, Vicente; Guzmán-Miranda, Hipólito; Nápoles, J.; Torralba Silgado, Antonio Jesús; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC192: Ingeniería Electrónica
VLSI circuits for space application must be protected by the insertion of massive redundancy. However, this increases silicon area and the production costs, therefore designers can often consider leaving some large, noncritical subcircuits unprotected. This paper presents how FT-UNSHADES, a nonintrusive tool for fault injection on emulated hardware, helps designers to select the proper level of protection in every subcircuit. Using FT-UNSHADES, a test procedure is proposed that provides: 1) information about the quality of the test vectors, 2) a proper estimation of the number of injected faults required to get confidence about the results of a fault injection campaign, and 3) information about the criticality of individual subcircuits by selective fault injection campaigns. In addition, FT-UNSHADES allows the insertion of multi-bit flips. This test procedure has been applied to three different, protected and unprotected, versions of the well-known Leon2 processor, and the results are discussed here
Pulsed Laser SEU Cross Section Measurement Using Coincidence Detector
(Institute of Electrical and Electronics Engineers (IEEE), 2008-09) Palomo Pinto, Rogelio; Mogollón, J.M.; Nápoles, J.; Guzmán-Miranda, Hipólito; Pérez Vega-Leal, Alfredo; Aguirre Martínez, M.A.; Moreno, P.; Méndez, C.; Vázquez de Aldana, J.R.; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Ministerio de Industria, Turismo y Comercio. España; Universidad de Sevilla. TIC-192 : Ingeniería Electrónica
This work presents the determination of a Pulsed Laser SEU Cross-Section (Count Statistics). In this work, a coincidence detector has been used to count fault events by comparing the digital VLSI circuit under test with a replica of the design running on a control FPGA. A SEU is declared when a specific fault pattern is detected. The target chip design generates specific fault patterns under pulsed laser shinning. Sweeping the laser energy on a flip flop of a Shift Register, data for a cross section analysis it is obtained. The coincidence detector was previously tested in a preliminary radiation test, so all the lessons learned in the design of radiation test can be translated for future works. In this work it has been used the pulsed laser facilities of Spanish National Laser Center in Salamanca. © 2008 IEEE.
An inexpensive arbitrary waveform neurostimulator for the selective activation of neurons in retinal prosthesis
(Universidad Politécnica de Cartagena, 2023-12-18) Jiménez Fernández, P.; Guzmán-Miranda, Hipólito; Barriga-Rivera, Alejandro; Universidad de Sevilla. Departamento de Física Aplicada III; Universidad de Sevilla. Departamento de Ingeniería Electrónica; European Union (UE); Agencia Estatal de Investigación. España; Foundation for Fighting Blindness (FUNDALUCE)
This contribution presents a two-channel inexpensive arbitrary waveform neurostimulator based on a Raspberry Pi microcomputer platform and a Howland voltage-to-current converter. The system has been designed to enable the delivery of common stimulation strategies used in visual prosthesis research.
A Virtual Reality Prototype as a Tool Against Verbal Abuse in Classrooms: A Multidisciplinary Approach
(Science and Technology Publications, Lda, 2024) Fondón García, Irene; Elena Pérez, María del Mar; Jiménez Lagares, Irene; Gaytán Guía, Susana Pilar; Universidad de Sevilla. Departamento de Fisiología; Universidad de Sevilla. Departamento de Psicología Evolutiva y de la Educación; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. Departamento de Teoría de la Señal y Comunicaciones
The exploration of affective response and its vegetative correlate to verbal abuse (VA) is a relevant research area to prevent bullying at schools. Taking advantage of the possibilities that virtual reality offers regarding to immersion in non-real environments inducing feelings in the users, this paper presents a virtual reality application focused on the study of VA in a school context. The versatility of the proposed project is directly related to its applicability. It has been designed under the premises of the psycho-neural effect of VA. The tool is intended to be used under professional and parental supervision, to perform experiments regarding bulling awareness. In this first stage, the authors propose a prototype that will be optimized and upgraded in future versions.
A scientific approach in wind energy courses for electrical engineers
(Institute of Electrical and Electronics Engineers, 2016) Durán, Mario J.; Barrero, Federico; González Prieto, Ignacio; Guzmán, Hugo; Pozo, A.; Bermúdez Guzmán, Mario; Martín Torres, Cristina; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. Departamento de Ingeniería Eléctrica; Universidad de Sevilla. TIC201: ACE-Ti; Universidad de Sevilla. TEP196: Sistemas de Energía Eléctrica
Teaching and research are joint activities at University level, but in many cases it is found that both activities have a poor connection. While the scientific method based on well-known steps is commonly applied at research level, this methodology and the associated know-how are rarely integrated in degree courses. This work describes the integration of theory, simulation, lab-scale experiments and industrial developments in wind energy courses for electric engineers. The proposed methodology reuses the knowledge from the research that is performed at University level to bring the students the latest industry developments and scientific trends with a scientific approach in multidisciplinary wind energy courses.
Comparative study of DTC and RFOC methods for the open-phase fault operation of a 5-phase induction motor drive
(Institute of Electrical and Electronics Engineers, 2015) Bermúdez Guzmán, Mario; Guzmán, Hugo; González Prieto, Ignacio; Barrero, Federico; Durán, Mario J.; Kestelyn, Xavier; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Junta de Andalucía; Ministerio de Economía y Competitividad (MINECO). España; Universidad de Sevilla. TIC201: ACE-Ti
Direct Torque Control (DTC) technique has been applied in recent times in high performance five-phase induction motor drives during the normal operation of the system. The use of DTC in the multiphase area is far from becoming a reality because it has not been used in competitive multiphase applications where the fault operation needs to be considered. The authors have successfully tested the ability of DTC controllers to manage the open-phase fault operation in a fivephase induction motor drive. However, the conclusion of the mentioned study must be completed comparing the obtained results with other mature alternatives based on field oriented controllers. This paper focuses on the comparative analysis of DTC and Rotor Field Oriented Control (RFOC) when an openphase fault appears in the five-phase induction motor drive. Simulation results are provided to compare the performance of the system using these control alternatives.
Open-Phase Fault Operation of 5-Phase Induction Motor Drives using DTC Techniques
(Institute of Electrical and Electronics Engineers, 2015) Bermúdez Guzmán, Mario; González Prieto, Ignacio; Barrero, Federico; Durán, Mario J.; Kestelyn, Xavier; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Junta de Andalucía; Ministerio de Economía y Competitividad (MINECO). España; Universidad de Sevilla. TEP196: Sistemas de Energía Eléctrica; Universidad de Sevilla.TIC-201: ACE-TI
Direct torque control (DTC) is extensively used in conventional three-phase drives as an alternative to field-oriented control methods. The standard DTC technique was originally designed to regulate two independent variables using hysteresis controllers. Recent works have extended the procedure for fivephase drives in healthy operation accounting for the additional degrees of freedom. Although one of the main advantages of multiphase machines is the ability to continue the operation in faulty conditions, the utility of DTC after the appearance of a fault has not been covered in the literature yet. This paper analyses the operation of a five-phase induction motor drive in faulty situation using a DTC controller. An open-phase fault condition is considered, and simulation results are provided to study the performance of the drive, comparing with the behavior during healthy state.
Monte Carlo simulation applicable for predictive algorithm analysis in aerospace
(Springer, 2023) Bautista Hernández, Jorge; Martín Prats, María de los Ángeles; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC109: Tecnología Electrónica
Safety investigations about electrical wiring harness caused by failures in electrical systems establish that origin of these accidents are related to electrical installation. Predictive techniques which mitigate and reduce risk of the occurrence of errors to enhance safety shall be considered. The development of machine learning has evolved towards the creation of innovative predictive algorithms which show high performance in data analysis and making predictions in the context of artificial intelligence. The Monte Carlo approach is used to validate the model performance. In this paper, Monte Carlo simulation was used to evaluate the level of the uncertainty of the selected parameters over 1000 runs. This study analyzes the reliability of the predictive algorithm in order to be implemented as an automatic error predictor in aerospace. The results obtained are within the expected range suggesting that the model used is accurate and reliable.
Rail to Rail Fully Differential Track and Hold Based on Clocked Differential Difference Amplifier Using Resistive Local Common Mode Feedback
(2008-11) Ramírez Angulo, Jaime; Luján Martínez, Clara Isabel; Rubia Marcos, Carlos; González Carvajal, Ramón; López Martín, Antonio; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC192: Ingeniería Electrónica
An efficient clocked class AB fully differential rail to rail differential difference amplifier is introduced. It is based on a two stage operational amplifier architecture with resistive local common mode feedback, floating gate transistors in the input stages and in the common mode feedback network. Its application in fully differential rail to rail high performance sample and hold circuits is discussed. Other applications discussed include fully differential buffers and single ended to fully differential converters with enable input. Experimental results of a test chip prototype fabricated in 0.5μm CMOS technology validate the proposed scheme. The fabricated track and hold has an SFDR=69.5dB with a clock frequency of 2MHz and 2Vpp, 200KHz input signals.
Adaptive Miller Compensation under Extreme Load Variations in IC-LDO regulators
(2018-11-14) Hinojo Montero, José María; Luján Martínez, Clara Isabel; Torralba Silgado, Antonio Jesús; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC192: Ingeniería Electrónica
A new frequency compensation technique for output buffers able to manage a wide range of loads, is proposed in this paper. To improve the stability, this technique implements a variable zero nulling resistor in a classical Miller compensation. A replica circuit senses the operating region of the output stage and generates the required value of the nulling resistor. In order to validate the effectiveness of the proposed technique, an Internally Compensated Low Dropout (IC-LDO) regulator based on a classical topology has been chosen and designed in a 65 nm standard CMOS technology. Results show that the proposed compensation scheme improves the Phase Margin of the IC- LDO regulator keeping it higher than 54o for load currents from 0 to 100mA at the cost of increasing only 10% the total quiescent power consumption and negligible area.
IC-LDO Regulator with 600 nA Quiescent Current Using a Class AB Buffer
(2018-11-14) Hinojo Montero, José María; Luján Martínez, Clara Isabel; López Morillo, Enrique; Torralba Silgado, Antonio Jesús; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC192: Ingeniería Electrónica
An ultra-low power Internally Compensated Low- Dropout (IC-LDO) regulator with a quiescent current consumption lower than 600 nA is proposed. It is based on the classical IC-LDO topology, which has been modified to include a class AB buffer between the output of the error amplifier and the gate of the pass transistor (MPASS). This way, a fast charge/discharge of its parasitic capacitance is achieved with the inherent low quiescent power consumption of class AB circuits. The proposed regulator has been fabricated in a standard 0.18- μm CMOS technology. Experimental results show that the proposed regulator has a Figure of Merit in the state of the art.
COTS Tolerant to Total Ionizing Dose (TID): AlGaN/GaNbased transistor 10 KeV X-ray Analysis
(IOP Science, 2022) Bôas, Alexis C.Vilas; Alberton, Saulo G.P.N.; de Melo, Marco Antônio Assis; Santos, Roberto Baginski Batista; Giacomini, R. Camargo; Medina, Nilberto H.; Seixas, Luís Eduardo; Finco, S.; Palomo Pinto, Rogelio; Guazzelli, Marcilei Aparecida; Universidad de Sevilla. Departamento de Ingeniería Electrónica; Universidad de Sevilla. TIC192: Ingeniería Electrónica
Gallium nitride commercial transistors (GaN FET) are great candidates as power devices tolerant to the effects of Total ionizing dose (TID). Therefore, we have evaluated its robustness by analysing parameters in its characteristic parameters. Devices were exposed to a 10 keV X-ray source accumulating a total of 350 krad(Si). However, results indicate that the tested components are more tolerant to the effects of TID when in on-state mode rather than the off-mode, that is, when the device is working, which is good news for COTS applications in environments subject to the effects of ionizing radiation.

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