Capítulos (Instituto de Microelectrónica de Sevilla (IMSE-CNM))

URI permanente para esta colecciónhttps://hdl.handle.net/11441/10970

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Mostrando 1 - 7 de 7

Fire detection with a frame-less vision sensor working in the NIR band
(Universidad de Coimbra, 2014) Leñero Bardallo, Juan Antonio; Fernández Berni, Jorge; Carmona Galán, Ricardo; Häfliger, Philipp; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This paper draws the attention of the community about the capabilities of an emerging generation of bio-inspired vision sensors to be used in fire detection systems. Their principle of operation will be described. Moreover experimental results showing the performance of an event-based vision sensor will be provided. The sensor was intended to monitor flames activity without using optic filters. In this article, we will also extend this preliminary work and explore how its outputs can be processed to detect fire in the environment
Tools for Automated Design of ΣΔ Modulators
(Springer, 1997) Medeiro Hidalgo, Fernando; Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications for the building blocks used in the modulators, and optimum sizes for the components in these blocks. Optimization procedures at the modulator level are equation-based, while procedures at the cell level are simulation-based. The toolset incorporates also an advanced ΣΔ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: 1) a 17bit@40kHz output rate fourth-order low-pass modulator; and 2) a 8bit@1.26MHz central freq@10kHz bandwidth band-pass modulator. The first uses SC fully-differential circuits in a 1.2μm CMOS double-metal double-poly technology. The second uses SI fully-differential circuits in a 0.8μm CMOS double-metal single-poly technology.
Towards an ultra‐low‐power low‐cost wireless visual sensor node for fine‐grain detection of forest fires
(Universidade de Coimbra, 2014) Fernández Berni, Jorge; Carmona Galán, Ricardo; Leñero Bardallo, Juan Antonio; Kleihorst, Richard; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Advances in electronics, sensor technologies, embedded hardware and software are boosting the application scenarios of wireless sensor networks. Specifically, the incorporation of visual capabilities into the nodes means a milestone, and a challenge, in terms of the amount of information sensed and processed by these networks. The scarcity of resources – power, processing and memory – imposes strong restrictions on the vision hardware and algorithms suitable for implementation at the nodes. Both, hardware and algorithms must be adapted to the particular characteristics of the targeted application. This permits to achieve the required performance at lower energy and computational cost. We have followed this approach when addressing the detection of forest fires by means of wireless visual sensor networks. From the development of a smoke detection algorithm down to the design of a low‐power smart imager, every step along the way has been influenced by the objective of reducing power consumption and computational resources as much as possible. Of course, reliability and robustness against false alarms have also been crucial requirements demanded by this specific application. All in all, we summarize in this paper our experience in this topic. In addition to a prototype vision system based on a full‐custom smart imager, we also report results from a vision system based on ultra‐low‐power low‐cost commercial imagers with a resolution of 30×30 pixels. Even for this small number of pixels, we have been able to detect smoke at around 100 meters away without false alarms. For such tiny images, smoke is simply a moving grey stain within a blurry scene, but it features a particular spatio‐temporal dynamics. As described in the manuscript, the key point to succeed with so low resolution thus falls on the adequate encoding of that dynamics at algorithm level
A focal plane processor for continuous-time 1-D optical correlation applications
(Springer, 2011) Liñán Cembrano, Gustavo; Carranza González, Luis; Alexandre, B.; Rodríguez Vázquez, Ángel Benito; Fuente, Pablo de la; Morlanes, Tomás; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This chapter describes a 1-D Focal Plane Processor, which has been designed to run continuous-time optical correlation applications. The chip contains 200 sensory processing elements, which acquire light patterns through a 2mm ×10.9μm photodiode. The photogenerated current is scaled at the pixel level by five independent 3-bit programmable-gain current scaling blocks. The correlation patterns are defined as five sets of two hundred 3-bit numbers (from 0 to 7), which are provided to the chip through a standard I2C interface. Correlation outputs are provided in current form through 8-bit programmable gain amplifiers (PGA), whose configurations are also defined via I2C. The chip contains a mounting alignment help, which consists of three rows of 100 conventional active pixel sensors (APS) inserted at the top, middle and bottom part of the main photodiode array. The chip has been fabricated in a standard 0.35μm CMOS technology and its maximum power consumption is below 30mW. Experimental results demonstrate that the chip is able to process interference patterns moving at an equivalent frequency of 500kHz.
BandPass Sigma-Delta Analog-to-Digital Converters
(Springer, 2003) Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Medeiro Hidalgo, Fernando; Río Fernández, Rocío del; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow bandwidth. Thus, BPΣΔMs have much in common with their lowpass counterparts - whose properties have been covered in previous Chapters of this book. However, there are some issues which are peculiar to BPΣΔ-ADCs. This Chapter is devoted to the description of these issues. In Section 11.2, digital radio receivers are revised, pointing out the necessity for an ADC at the IF location. Section 11.3 and Section 11.4 explain the basic concepts and architectural issues of BPΣΔ-ADCs. The problems derived from circuit implementation are treated in Section 11.5. Finally, Section 11.6 summarizes the performance of state-of-the-art BPΣΔ-ADCs.
Image Feature Extraction Acceleration
(Springer, 2016) Fernández Berni, Jorge; Suárez Cambre, Manuel; Carmona Galán, Ricardo; Brea Sánchez, Víctor Manuel; Río Fernández, Rocío del; Cabello, D.; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Image feature extraction is instrumental for most of the best-performing algorithms in computer vision. However, it is also expensive in terms of computational and memory resources for embedded systems due to the need of dealing with individual pixels at the earliest processing levels. In this regard, conventional system architectures do not take advantage of potential exploitation of parallelism and distributed memory from the very beginning of the processing chain. Raw pixel values provided by the front-end image sensor are squeezed into a high-speed interface with the rest of system components. Only then, after deserializing this massive dataflow, parallelism, if any, is exploited. This chapter introduces a rather different approach from an architectural point of view. We present two Application-Specific Integrated Circuits (ASICs) where the 2-D array of photo-sensitive devices featured by regular imagers is combined with distributed memory supporting concurrent processing. Custom circuitry is added per pixel in order to accelerate image feature extraction right at the focal plane. Specifically, the proposed sensing-processing chips aim at the acceleration of two flagships algorithms within the computer vision community: the Viola-Jones face detection algorithm and the Scale Invariant Feature Transform (SIFT). Experimental results prove the feasibility and benefits of this architectural solution.
Background Digital Calibration of Comparator Offsets in Pipeline ADCs
(Institute of Electrical and Electronics Engineers, 2015) Ginés Arteaga, Antonio José; Peralías Macías, Eduardo; Rueda Rueda, Adoración; Junta de Andalucía; Gobierno de España
This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

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