Ponencias (Electrónica y Electromagnetismo)
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Ponencia Combining CRYSTALS-Kyber Homomorphic Encryption with Garbled Circuits for Biometric Authentication(Institute of Electrical and Electronics Engineers, 2024-12-11) Arjona, Rosario; Franco Moreno, Claudia; Román Hajderek, Roberto; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Agencia Estatal de Investigación. EspañaBiometric data are sensitive according to personal data regulations and ISO/IEC 24745. In a biometric recognition system, biometric data should be protected from their generation to their comparison. In this work, we combine postquantum homomorphic encryption using CRYSTALS-Kyber (the base post-quantum algorithm of the FIPS 203 standard for module-lattice-based key-encapsulation mechanism, recently approved by the NIST) with Garbled Circuits, which allow different parties to compute the result of an operation from private inputs. We propose a protected biometric authentication scheme in which homomorphic encryption with CRYSTALS-Kyber public-key encryption computes the difference between the reference and a query, and a Garbled Circuit (GC) performs the comparison with a threshold. Two GC frameworks, TinyGarble (based on Verilog) and TinyGarble2 (based on C++), are employed to design a privacy-preserving face authentication system with FaceNet embeddings. The two frameworks are compared in terms of design and computation costs. In any case, the authentication takes, approximately, 0.5 seconds.Ponencia Hardware Security for eXtended Merkle Signature Scheme Using SRAM-based PUFs and TRNGs(Institute of Electrical and Electronics Engineers Inc., 2020-12-18) Román Hajderek, Roberto; Arjona, Rosario; Arcenegui Almenara, Javier; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Agencia Estatal de Investigación. España; Junta de AndalucíaDue to the expansion of the Internet of Things (IoT), there is an increasing number of interconnected devices around us. Integrity, authentication and non-repudiation of data exchanged between them is becoming a must. This can be achieved by means of digital signatures. In recent years, the eXtended Merkle Signature Scheme (XMSS) has gained popularity in embedded systems because of its simple implementation, post-quantum security, and minimal security assumptions. From a hardware point of view, the security of digital signatures strongly depends on how the private keys are generated and stored. In this work, we propose the use of SRAMs as True Random Generators (TRNGs) and Physically Unclonable Functions (PUFs) to generate and reconstruct XMSS keys in a trusted way. We achieve a low-cost solution that only adds lightweight operations to the signature itself, such as repetition decoding and XORing, and does not require additional hardware (like secure non-volatile memories) since the manufacturing variations of the SRAM inside the IoT device are exploited. As a proof of concept, the solution was implemented in an IoT board based on the ESP32 microcontroller.Ponencia Secure management of IoT devices based on blockchain non-fungible tokens and physical unclonable functions(Springer Nature, 2020-10) Arcenegui Almenara, Javier; Arjona, Rosario; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Agencia Estatal de Investigación. España; Junta de AndalucíaOne of the most extended applications of blockchain technologies for the IoT ecosystem is the traceability of the data and operations generated and performed, respectively, by IoT devices. In this work, we propose a solution for secure management of IoT devices that participate in the blockchain with their own blockchain accounts (BCAs) so that the IoT devices themselves can sign transactions. Any blockchain participant (including IoT devices) can obtain and verify information not only about the actions or data they are taking but also about their manufacturers, managers (owners and approved), and users. Non Fungible Tokens (NFTs) based on the ERC-721 standard are proposed to manage IoT devices as unique and indivisible. The BCA of an IoT device, which is defined as an NFT attribute, is associated with the physical device since the secret seed from which the BCA is generated is not stored anywhere but a Physical Unclonable Function (PUF) inside the hardware of the device reconstructs it. The proposed solution is demonstrated and evaluated with a low-cost IoT device based on a Pycom Wipy 3.0 board, which uses the internal SRAM of the microcontroller ESP-32 as PUF. The operations it performs to reconstruct its BCA in Ethereum and to carry out transactions take a few tens of milliseconds. The smart contract programmed in Solidity and simulated in Remix requires low gas consumption.Ponencia A dedicated hardware implementation for biometric recognition based on finger veins(Institute of Electrical and Electronics Engineers Inc., 2019-11) Arjona, Rosario; Costas, J.; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Agencia Estatal de Investigación. EspañaNowadays, there is an increasing demand of security devices which include biometric authentication. Biometric recognition based on finger veins is very suitable for lightweight devices because it provides distinctiveness and the acquisition can employ small-size camera and low-cost sensors. Among the extraction techniques of features for finger veins, Wide Line Detector offers a good trade-off between recognition accuracy and computational complexity. A generic VHDL description has been developed for this feature extraction technique and the matching of the binary feature images. Implementation results on a Zynq 7020 FPGA are provided.Artículo Efficient realisation of MOS-NDR threshold logic gates(Wiley Open Access, 2009-11-05) Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Gobierno de España; Junta de AndalucíaA novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.Ponencia Securing Minutia Cylinder Codes for Fingerprints through Physically Unclonable Functions: An Exploratory Study(IEEE, 2018-07-16) Arjona, Rosario; Prada Delgado, Miguel Ángel; Baturone Castillo, María Iluminada; Ross, Arun; Ministerio de Economía y Competitividad (MINECO). España; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER); Consejo Superior de Investigaciones Científicas (CSIC); National Science Foundation (NSF). United States; Universidad de SevillaA number of personal devices, such as smartphones, have incorporated fingerprint recognition solutions for user authentication purposes. This work proposes a dual-factor fingerprint matching scheme based on P-MCCs (Protected Minutia Cylinder-Codes) generated from fingerprint images and PUFs (Physically Unclonable Functions) generated from device SRAMs (Static Random Access Memories). Combining the fingerprint identifier with the device identifier results in a secure template satisfying the discriminability, irreversibility, revocability, and unlinkability properties, which are strongly desired for data privacy and security. Experiments convey the benefits of the proposed dual-factor authentication mechanism in enhancing the security of personal devices that utilize biometric authentication schemes.Ponencia Demonstrator of a fingerprint recognition algorithm into a low-power microcontroller(IEEE, 2017-11) Arcenegui Almenara, Javier; Arjona, Rosario; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y ElectromagnetismoA demonstrator has been developed to illustrate the performance of a lightweight fingerprint recognition algorithm based on the feature QFingerMap16, which is extracted from a window of the directional image centered at the convex core of the fingerprint. The algorithm has been implemented into a lowpower ARM Cortex-M3 microcontroller included in a Texas Instruments LaunchPad CC2650 evaluation kit. It has been also implemented in a Raspberry Pi 2 so as to show the results obtained at the successive steps of the recognition process with the aid of a Graphical User Interface (GUI). The algorithm offers a good tradeoff between power consumption and recognition accuracy, being suitable for authentication on wearables.Ponencia A Dual-Factor Access Control System Based on Device and User Intrinsic Identifiers(IEEE, 2016-12) Arjona, Rosario; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y ElectromagnetismoThis paper proposes an access control system based on the simultaneous authentication of what the user has and who the user is. At enrollment phase, the wearable access device (a smart card, key fob, etc.) stores a template that results from the fusion of the intrinsic device identifier and the user biometric identifier. At verification phase, both the device and user identifiers are extracted and matched with the stored template. The device identifier is generated from the start-up values of the SRAM in the device hardware, which are exploited as a Physically Unclonable Function (PUF). Hence, if the device hardware is cloned, the authentic identifier is not generated. The user identifier is obtained from level-1 fingerprint features (directional image and singular points), which are extracted from the fingerprint images captured by the sensor in the access device. Hence, only genuine users with genuine devices are authorized to access and no sensitive information is stored or travels outside the access device. The proposal has been validated by using 560 fingerprints acquired in live by an optical sensor and 560 SRAM-based identifiers.Ponencia Dedicated Hardware IP Module for Fingerprint Recognition(IEEE, 2015-08-06) Martínez Rodríguez, Macarena Cristina; Arjona, Rosario; Brox Jiménez, Piedad; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Gobierno de España; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER); Universidad de SevillaThis work presents a dedicated hardware IP module for fingerprints recognition based on a feature, named QFingerMap, which is very suitable for VLSI design. FPGA implementation results of the IP module are given. A demonstrator has been developed to evaluate the IP module behavior in a real scenario.Ponencia A Fingerprint Retrieval Technique Using Fuzzy Logic-Based Rules(Springer, 2015) Arjona, Rosario; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Economía y Competitividad (MINECO). España; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)This paper proposes a global fingerprint feature named QFingerMap that provides fuzzy information about a fingerprint image. A fuzzy rule that combines information from several QFingerMaps is employed to register an individual in a database. Error and penetration rates of a fuzzy retrieval system based on those rules are similar to other systems reported in the literature that are also based on global features. However, the proposed system can be implemented in hardware platforms of very much lower computational resources, offering even lower processing time.Ponencia Hardware Implementation of a Biometric Recognition Algorithm based on In-Air Signature(IEEE, 2015-06-01) Arjona, Rosario; Romero Moreno, Rocío; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Economía y Competitividad (MINECO). España; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)This paper presents the design of a prototype for a wearable device that implements a recognition system based on in-air signature into a FPGA that receives data from a 3-axis accelerometer. The Dynamic Time Warping (DTW) algorithm has been analyzed and simplified to reduce the complexity of the hardware architecture that implements the matching in the FPGA. Despite simplification, accuracy of the recognition is maintained and the Equal Error Rate, EER, is 4.21% considering a public database with 120 in-air signatures. A prototype based on a Spartan 6 LX9 microboard connected to an ultralow power ADXL345 accelerometer has been developed. Performance of the prototype working with in-air signatures has been verified with a script developed in Matlab-Simulink. The execution time for matching is 22 ms and the estimated average power consumption of the matching in the FPGA is 26 mW.Ponencia Use Case Examples of Ethereum Non-Fungible Tokens Tied to Assets Using ERC-4519(IEEE, 2023) Arcenegui Almenara, Javier; Arjona, Rosario; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y ElectromagnetismoEthereum is a dynamic blockchain that grows every day thanks to a community that creates and decides on various of its issues. The community participates through Ethereum Improvement Proposals (EIPs) at many levels, from proposals that describe new standards for the creation of new tokens to proposals that define new ways for the Ethereum main network to generate new blocks. This paper describes how an Ethereum Request for Comments (ERC)-type EIP, the ERC4519, was proposed last year to standardize the way to define non-fungible tokens (NFTs) representing assets that can generate their own Ethereum addresses and obey users and owners. Advantages provided by ERC-4519 in several use cases are illustrated. The examples show the facilities and the security improvements introduced in the management of both physical and digital assets by their owners and users. Particularly, use cases with physical assets such as IoT devices are illustrated.Ponencia Vertically Stacked CMOS-compatible Photodiodes for Scanning Electron Microscopy(Institute of Electrical and Electronics Engineers (IEEE), 2020) Gontard, Lionel C.; Leñero Bardallo, Juan Antonio; Varela Feria, Francisco M.; Carmona Galán, Ricardo; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Agencia Estatal de Investigación. España; Universidad de Cádiz; European Union (UE). H2020; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)This paper reports the use of vertically stacked photodiodes as compact solid-state spectrometers for transmission scanning electron microscopy. SEM microscopes operate by illuminating the sample with accelerated electrons. They can have one or more solid-state sensors. In this work we have tested a set of stacked photodiodes fabricated in a standard 180nm HV-CMOS technology without process modifications. We have measured their sensitivity to electron irradiation in the energy range between 10keV and 30keV. We have also assessed their radiation hardness. The experiments are compared with Monte Carlo simulations to investigate their spectral sensitivity.Ponencia VersaTile Convolutional Neural Network Mapping on FPGAs(Institute of Electrical and Electronics Engineers (IEEE), 2020) Muñío Gracia, A.; Fernández Berni, Jorge; Carmona Galán, R.; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; European Union (UE). H2020; Ministerio de Economia, Industria y Competitividad (MINECO). España; Office of Naval Research (ONR). United StatesConvolutional Neural Networks (ConvNets) are directed acyclic graphs with node transitions determined by a 1 set of configuration parameters. In this paper, we describe a 2 dynamically configurable hardware architecture that enables 4 3 data allocation strategy adjustment according to ConvNets layer 5 characteristics. The proposed flexible scheduling solution allows 6 the accelerator design to be portable across various scenarios of 7 computation and memory resources availability. For instance, 8 FPGA block-RAM resources can be properly balanced for 9 optimization of data distribution and minimization of off-chip 10 memory accesses. We explore the selection of tailored scheduling policies that translate into efficient on-chip data reuse and hence lower energy consumption. The system can autonomously adapt its behavior with no need of platform reconfiguration nor user supervision. Experimental results are presented and compared with state-of-the-art accelerators.Ponencia Static Linearity BIST for Vcm-based Switching SAR ADCs Using a Reduced-code Measurement Technique(Institute of Electrical and Electronics Engineers (IEEE), 2020) Feitoza, Renato S.; Barragan, Manuel J.; Ginés Arteaga, Antonio José; Mir, Salvador; Universidad de Sevilla. Departamento de Electrónica y ElectromagnetismoThis work presents a reduced-code strategy for the static linearity self-testing of Vcm -based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the application of these techniques for the Vcm-based SAR ADC topology and present a practical BIST implementation based on an embedded incremental ADC. Electrical simulation results at transistor level are presented to validate the feasibility of the proposed on-chip reduced-code static linearity test.Ponencia On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter(Institute of Electrical and Electronics Engineers (IEEE), 2020) Feitoza, Renato S.; Barragan, Manuel J.; Ginés Arteaga, Antonio José; Mir, Salvador; Universidad de Sevilla. Departamento de Electrónica y ElectromagnetismoThis paper describes a BIST technique for the static linearity test of Vcm-based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the Vcm-based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.Artículo Dual-polarization reflectarray in Ku-band based on two layers of dipole-arrays for a transmit-receive satellite antenna with South American coverage(Institute of Electrical and Electronics Engineers (IEEE), 2017) Encinar, José A.; Florencio Díaz, Rafael; Arrebola, Manuel; Salas, Miguel A.; Barba, Mariano; Page, Juan E.; Rodríguez Boix, Rafael; Toso, Giovanni; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Economía y Competitividad (MINECO). España; Junta de Andalucía; European Space Agency (ESA)A 1.1-m reflectarray antenna has been designed, manufactured and tested to fulfil the requirements of a satellite antenna in Ku-band that provides South American coverage in Tx and Rx. The reflectarray cells consist of four dipoles for each polarization in two dielectric layers, which were selected because of their simplicity and high performance. The dipole dimensions are optimized in all the reflectarray cells to accomplish the prescribed radiation patterns, by iteratively calling an analysis routine based on MoM-SD and local periodicity. The measured radiation patterns of the manufactured antenna have been satisfactorily compared with simulations and with a 3-layer reflectarray previously designed for the same mission.Ponencia Using physical unclonable functions for internet-of-thing security cameras(Springer, 2018) Arjona, Rosario; Prada Delgado, Miguel Ángel; Arcenegui Almenara, Javier; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Economía y Competitividad (MINECO). España; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER); Consejo Superior de Investigaciones Científicas (CSIC); Universidad de SevillaThis paper proposes a low-cost solution to develop IoT security cameras. Integrity and confidentiality of the image data are achieved by cryptographic modules that implement symmetric key-based techniques which are usually available in the hardware of the IoT cameras. The novelty of this proposal is that the secret key required is not stored but reconstructed from the start-up values of a SRAM in the camera hardware acting as a PUF (Physical Unclonable Function), so that the physical authenticity of the camera is also ensured. The start-up values of the SRAM are also exploited to change the IV (Initialization Vector) in the encryption algorithm. All the steps for enrollment and normal operation can be included in a simple firmware to be executed by the camera. There is no need to include specific hardware but only a SRAM is needed which could be powered down and up by firmware.Ponencia Demo: Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision(ACM Digital Library, 2018) Carmona Galán, Ricardo; Fernández Berni, Jorge; Rodríguez Vázquez, Ángel Benito; López Martínez, Paula; Brea Sánchez, Víctor Manuel; Cabello Ferrer, D.; Zapata Pérez, J.; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Economia, Industria y Competitividad (MINECO). España; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER); Junta de Andalucía; Agencia Ejecutiva Europea de Investigación (EU-REA); European Union (UE). H2020iCaveats is a Project on the integration of components and architectures for embedded vision in transport and security applications. A compact and efficient implementation of autonomous vision systems is difficult to be accomplished by using the conventional image processing chain. In this project we have targeted alternative approaches, that exploit the inherent parallelism in the visual stimulus, and hierarchical multilevel optimization. A set of demos showcase the advances at sensor level, in adapted architectures for signal processing and in power management and energy harvesting.Ponencia Self-Testing Analog Spiking Neuron Circuit(Institute of Electrical and Electronics Engineers, 2019) El-Sayed, Sarah A.; Camuñas Mesa, Luis Alejandro; Linares Barranco, Bernabé; Stratigopoulos, Haralampos G.; Universidad de Sevilla. Departamento de Electrónica y ElectromagnetismoHardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35μm CMOS technology.