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ASIC implementation of an ARM - based system on chip
dc.creator | Granado Romero, Joaquín | es |
dc.creator | Chávez Orzaez, Jorge Jesús | es |
dc.creator | Colodro Ruiz, Francisco | es |
dc.creator | Torralba Silgado, Antonio Jesús | es |
dc.creator | García Franquelo, Leopoldo | es |
dc.creator | Ramos, E. | es |
dc.creator | Hidalgo, A. | es |
dc.creator | Tortolero, A. | es |
dc.creator | Ruiz, F. | es |
dc.date.accessioned | 2015-03-26T08:28:23Z | |
dc.date.available | 2015-03-26T08:28:23Z | |
dc.date.issued | 2000 | es |
dc.identifier.uri | http://hdl.handle.net/11441/23548 | |
dc.description.abstract | This paper presents the hardware architecture of a System on Chip (SoC) implemented in an ASIC. It has been designed for a wide range of applications and will be used in a power line modem. A set of reusable cells based on AMBA standard has been also designed, included memory, interrupt controller and peripherals. Presented architecture implements an ARM© processor, a 32-bit RISC processor which is becoming a RISC standard. | en |
dc.format | application/pdf | es |
dc.language.iso | eng | en |
dc.relation.ispartof | Design of Circuits and Integrated Systems, 567-570. Montpellier, Francia : DCIS | en |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | es |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | es |
dc.title | ASIC implementation of an ARM - based system on chip | en |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Ingeniería Electrónica | es |
dc.relation.publisherversion | 10.13140/2.1.1846.3681 | |
dc.identifier.idus | https://idus.us.es/xmlui/handle/11441/23548 |
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file_1.pdf | 200.3Kb | [PDF] | Ver/ | |