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dc.creatorRoshankumar, P.
dc.creatorRajeevan, P. P.
dc.creatorMathew, K.
dc.creatorGopakumar, K.
dc.creatorLeón Galván, José Ignacio
dc.creatorGarcía Franquelo, Leopoldo
dc.date.accessioned2015-03-23T12:27:57Z
dc.date.available2015-03-23T12:27:57Z
dc.date.issued2012-08
dc.identifier.issn0885-8993es
dc.identifier.urihttp://hdl.handle.net/11441/23525
dc.description.abstractIn this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topol- ogy is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamen- tal) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This fea- ture improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor.en
dc.formatapplication/pdfes
dc.language.isoenges
dc.relation.ispartofIEEE Transactions on Power Electronics, 27(8), 3505-3512es
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectFlying capacitor (FC)es
dc.subjectH-bridgees
dc.subjectinduction motor drivees
dc.subjectmultilevel inverteres
dc.titleA five-level inverter topology with single-DC supply by cascading a flying capacitor inverter and an H-bridgees
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ingeniería Electrónicaes
dc.relation.publisherversion10.1109/TPEL.2012.2185714es
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6138327
dc.identifier.idushttps://idus.us.es/xmlui/handle/11441/23525

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