ListarArtículos (Arquitectura y Tecnología de Computadores) por materia "Address-event-representation"
Mostrando ítems 1-4 de 4
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Low Latency Event-Based Filtering and Feature Extraction for Dynamic Vision Sensors in Real-Time FPGA Applications
(IEEE Computer Society, 2019)Dynamic Vision Sensor (DVS) pixels produce an asynchronous variable-rate address-event output that represents brightness ...
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NAVIS: Neuromorphic Auditory VISualizer Tool
(Elsevier, 2017)This software presents diverse utilities to perform the first post-processing layer taking the neuromorphic auditory sensors ...
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Neuromorphic LIF Row-by-Row Multiconvolution Processor for FPGA
(IEEE Computer Society, 2018)Deep Learning algorithms have become state-of-theart methods for multiple fields, including computer vision, speech recognition, ...
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Stereo Matching in Address-Event-Representation (AER) Bio-Inspired Binocular Systems in a Field-Programmable Gate Array (FPGA)
(MDPI, 2019)In stereo-vision processing, the image-matching step is essential for results, although it involves a very high computational ...