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Ponencia
On the AER Convolution Processors for FPGA
(IEEE Computer Society, 2010)
Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these ...
Ponencia
AER tools for Communications and Debugging
(IEEE Computer Society, 2006)
Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them ...
Ponencia
AER image filtering
(SPIE Digital LIbrary, 2007-05)
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows realtime virtual massive connectivity among huge number of neurons located on different chips [1]. By exploiting ...
Ponencia
FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
(Springer, 2009)
Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In ...
Ponencia
High-speed image processing with AER-based components
(IEEE Computer Society, 2006)
A high speed sample image processing application using AER-based components is presented. The setup objective is to distinguish between two propellers of different shape rotating at high speed (around 1000 revolutions/sec) ...
Ponencia
An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata
(Springer, 2011)
Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event- Representation (AER) is a neuromorphic communication protocol for ...
Ponencia
Address-Event based Platform for Bio-inspired Spiking Systems
(SPIE Digital LIbrary, 2007-05)
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows a real-time virtual massive connectivity between huge number neurons, located on different chips. By exploiting ...
Ponencia
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
(Neural Information Processing Systems Foundation, 2005)
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-eventrepresentation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a ...
Artículo
Diseño e implementación de un simulador software basado en el procesador MIPS32
(Universidad de Granada, 2015)
La arquitectura de computadores es una asignatura de gran importancia actualmente en las titulaciones de Informática. Pero en muchas ocasiones, los estudiantes tienen problemas para comprender la materia debido a la falta ...
Ponencia
Two Hardware Implementations of the Exhaustive Synthetic AER Generation Method
(Springer, 2005)
Address-Event-Representation (AER) is a communications protocol for transferring images between chips, originally developed for bio-inspired image processing systems. In [6], [5] various software methods for synthetic AER ...