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Mostrando ítems 1-10 de 43
Artículo
Compensation of PVT Variations in ToF Imagers with In-Pixel TDC
(MDPI, 2017)
The design of a direct time-of-flight complementary metal-oxide-semiconductor (CMOS) image sensor (dToF-CIS) based on a single-photon avalanche-diode (SPAD) array with an in-pixel time-to-digital converter (TDC) must ...
Artículo
A Wide Linear Dynamic Range Image Sensor Based on Asynchronous Self-Reset and Tagging of Saturation Events
(Institute of Electrical and Electronics Engineers, 2017)
We report a high dynamic range (HDR) image sensor with a linear response that overcomes some of the limitations of sensors with pixels with self-reset operation. It operates similar to an active pixel sensor, but its pixels ...
Artículo
A CMOS Digital SiPM With Focal-Plane Light-Spot Statistics for DOI Computation
(Institute of Electrical and Electronics Engineers, 2017)
Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to improve the quality of the positron emission tomography images affected by the parallax error. This ...
Artículo
Ultralow-power processing array for image enhancement and edge detection
(Institute of Electrical and Electronics Engineers, 2012)
This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a commercial 3-D through-silicon via stack. The array, which will constitute one of the fundamental ...
Artículo
Single-Exposure HDR Technique Based on Tunable Balance Between Local and Global Adaptation
(Institute of Electrical and Electronics Engineers, 2016)
This brief describes a high-dynamic-range technique that compresses wide ranges of illuminations into the available signal range with a single exposure. An online analysis of the image histogram provides the sensor with ...
Artículo
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose ...
Artículo
Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction
(Institute of Electrical and Electronics Engineers, 2017)
This paper introduces a CMOS vision sensor chip in a standard 0.18 μm CMOS technology for Gaussian pyramid extraction. The Gaussian pyramid provides computer vision algorithms with scale invariance, which permits having ...
Artículo
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)
This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple ...
Artículo
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of ...
Artículo
Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors
(Institute of Electrical and Electronics Engineers, 2017)
Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple ...