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Mostrando ítems 1-7 de 7
Ponencia
Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design
(1999)
This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier finite gain-bandwidth product and slew-rate during, unlike previous models, both the integration ...
Artículo
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-selta modulator for low-power high-linearity automotive aensor ASICs
(Institute of Electrical and Electronics Engineers, 2005)
This paper describes a 0.35-μm CMOS chopper-stabilized switched-capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple ...
Ponencia
A 0.13μm CMOS current steering D/A converter for PLC and VDSL applications
(2005)
This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification ...
Artículo
High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a high-level synthesis tool for ΣΔ Modulators (ΣΔMs) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques ...
Ponencia
A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology
(2000)
This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, ...
Artículo
Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+
(Institute of Electrical and Electronics Engineers, 2004)
We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) ...
Artículo
Analysis of error mechanisms in switched-current Sigma-Delta modulators
(Springer, 2004)
This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, ...