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Mostrando ítems 313-332 de 141277
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Artículo
A toponímia proto-histórica como ferramenta do arqueólogo? Comentários sobre uma relação problemática
(Universidad Complutense de Madrid : Servicio de Publicaciones, 2018)Estudos recentes têm vindo a destacar a toponímia proto-histórica enquanto ferramenta para a interpretação do registo ...
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Artículo
A K = 3 two-quasiparticle isomer in 98 Sr
(American Physical Society, 2002)The decay of on-line mass-separated 98 Rb to 98 Sr is studied by γ spectroscopy. The revised decay scheme ...
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Artículo
A propósito de la invalidez permanente: una reforma legal ad calendas graecas
(Universidad de Sevilla, 2023)Se analiza el prioritario desarrollo reglamentario del artículo 194.3 de la vigente Ley General de la Seguridad Social, ...
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Ponencia
A 0.13μm CMOS current steering D/A converter for PLC and VDSL applications
(2005)This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic ...
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Ponencia
A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter
(The International Society for Optical Engineering- SPIE, 2005)This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated ...
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Ponencia
A 0.18μm CMOS low-noise elliptic low-pass continuous-time filter
(Institute of Electrical and Electronics Engineers, 2005)This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline ...
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Ponencia
A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization
(The International Society for Optical Engineering - SPIE, 2005)This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive ...
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Ponencia
A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator
(Institute of Electrical and Electronics Engineers, 2004)This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a ...
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Ponencia
A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing
(Institute of Electrical and Electronics Engineers, 1998)An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips ...
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Artículo
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) ...
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Artículo
A 0.9-V 100-mu W Feedforward Adder-Less Inverter-Based MASH Delta Sigma Modulator With 91-dB Dynamic Range and 20-kHz Bandwidth
(Institute of Electrical and Electronics Engineers, 2018)A 0.9-V ΔΣ modulator integrated into a 0.18-μm CMOS technology for digitizing signals in low-power devices is presented ...
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Ponencia
A 1.25V FGMOS Filter Using Translinear Circuits
(IEEE Computer Society, 2001)This paper presents a new low voltage/low power filter design based on Floating-Gate MOS (FGMOS) transistors. FGMOS ...
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Artículo
A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings
(IEEE Computer Society, 2013)This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended ...
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Artículo
A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-Based CT MASH Delta Sigma Modulator
(Institute of Electrical and Electronics Engineers, 2020)We present in this brief a novel multi-stage noiseshaping (MASH) 3-1 continuous-time (CT) delta-sigma modulator (M) with ...
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Artículo
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ...
- Libro
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Artículo
A 12-Bit Low-Input Capacitance SAR ADC With a Rail-to-Rail Comparator
(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2023)The input capacitance of the SAR ADC is considered a drawback in many applications. In this paper, a 12-bit low-power SAR ...
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Ponencia
A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator
(Institute of Electrical and Electronics Engineers, 2007)This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, ...
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Artículo
A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology
(Institute of Electrical and Electronics Engineers, 1999)This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio ...