Simulation environment for an OFDM transmitter using UVM methodology

Abstract

The aim of this Project was to design a verification testbench using the Universal Verification Methodology standardized by Accellera. The HDL design I chose to verify was an OFDM transceiver written in VHDL according to the PRIME alliance specifications. The tools used were EDA proprietary software for hardware verification working in conjunction with Matlab. The strategy to develop the final testbench was based on a series of UVM testbenches, focusing on adding more UVM and verification functionality than the previous version. The final testbench was fully integrated with Matlab, which worked as a Golden model. The results of the project successfully prove that the UVM is a very scalable verification methodology, has the possibility to implement the most advanced verification measures and is simple to integrate with most modern technologies.