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Artículo

dc.creatorAguirre Echanove, Miguel Ángel
dc.creatorTombs, J. N.
dc.creatorBaena Lecuyer, Vicente
dc.creatorMora Jiménez, José Luis
dc.creatorCarrasco Solís, Juan Manuel
dc.creatorTorralba Silgado, Antonio Jesús
dc.creatorGarcía Franquelo, Leopoldoes
dc.date.accessioned2015-04-30T17:39:57Z
dc.date.available2015-04-30T17:39:57Z
dc.date.issued2005
dc.identifier.urihttp://hdl.handle.net/11441/24766
dc.description.abstractModern trends in technology require efficient control and processing platforms based on connected software-hardware subsystems. Due to their complexity and size, algorithms implemented on these platforms are difficult to test and verify. When these types of solution are being designed, it is necessary to provide information of the internal values of registers and memories of both the software and hardware during the execution of the complete system. The final architecture of the targeted design and its debugging capabilities strongly depends on how the hybrid system is connected and clocked. This article discusses different architectural strategies that have been adopted for a hybrid hardware-software platform, built ready for debugging, and that uses components that can be easily found with a few special features. All the solutions have been implemented and evaluated using the UNSHADES-2 framework.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherElsevieres
dc.relation.ispartofMicroprocessors and Microsystems, 29(2), 75-85es
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectHybrid systemen
dc.subjectCo-designen
dc.subjectCo-debugen
dc.subjectRapid prototypingen
dc.titleMicroprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systemses
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersion
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ingeniería Electrónicaes
dc.relation.publisherversion10.1016/j.micpro.2004.06.009es
dc.relation.publisherversionhttp://dx.doi.org/10.1016/j.micpro.2004.06.009
dc.identifier.doi10.1016/j.micpro.2004.06.009
dc.identifier.idushttps://idus.us.es/xmlui/handle/11441/24766

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