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dc.creatorGranado Romero, Joaquín es
dc.creatorChávez Orzaez, Jorge Jesús es
dc.creatorColodro Ruiz, Francisco es
dc.creatorTorralba Silgado, Antonio Jesús es
dc.creatorGarcía Franquelo, Leopoldo es
dc.creatorRamos, E. es
dc.creatorHidalgo, A. es
dc.creatorTortolero, A. es
dc.creatorRuiz, F. es
dc.date.accessioned2015-03-26T08:28:23Z
dc.date.available2015-03-26T08:28:23Z
dc.date.issued2000es
dc.identifier.urihttp://hdl.handle.net/11441/23548
dc.description.abstractThis paper presents the hardware architecture of a System on Chip (SoC) implemented in an ASIC. It has been designed for a wide range of applications and will be used in a power line modem. A set of reusable cells based on AMBA standard has been also designed, included memory, interrupt controller and peripherals. Presented architecture implements an ARM© processor, a 32-bit RISC processor which is becoming a RISC standard.en
dc.formatapplication/pdfes
dc.language.isoengen
dc.relation.ispartofDesign of Circuits and Integrated Systems, 567-570. Montpellier, Francia : DCISen
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacionales
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/es
dc.titleASIC implementation of an ARM - based system on chipen
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ingeniería Electrónicaes
dc.relation.publisherversion10.13140/2.1.1846.3681
dc.identifier.idushttps://idus.us.es/xmlui/handle/11441/23548

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