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Artículo
A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge
dc.creator | Kumar, P. Roshan | |
dc.creator | Rajeevan, P. P. | |
dc.creator | Mathew, K. | |
dc.creator | Gopakumar, K. | |
dc.creator | León Galván, José Ignacio | |
dc.creator | García Franquelo, Leopoldo | |
dc.date.accessioned | 2015-03-20T13:15:28Z | |
dc.date.available | 2015-03-20T13:15:28Z | |
dc.date.issued | 2014-03-03 | |
dc.identifier.issn | 0885-8993 | es |
dc.identifier.uri | http://hdl.handle.net/11441/23521 | |
dc.description.abstract | A three-level common-mode voltage eliminated in- verter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the re- sults are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be oper- ated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it pos- sible for a back-to-back grid-tied converter application, improved reliability, etc. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.relation.ispartof | IEEE Transactions on Power Electronics, 29(3), 1402-1409 | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Common-mode voltage elimination | es |
dc.subject | Hybrid mul- tilevel inverter | en |
dc.subject | Multilevel inverter | en |
dc.subject | Three-level inverter | en |
dc.title | A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Ingeniería Electrónica | es |
dc.relation.publisherversion | 10.1109/TPEL.2013.2262808 | es |
dc.relation.publisherversion | http://doi.org/10.1109/TPEL.2013.2262808 | |
dc.identifier.doi | http://doi.org/10.1109/TPEL.2013.2262808 | es |
dc.identifier.idus | https://idus.us.es/xmlui/handle/11441/23521 |
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