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Artículo
Design of two-stage class AB CMOS buffers: a systematic approach
dc.creator | López Martín, Antonio | |
dc.creator | Algueta Algueta, José María | |
dc.creator | Acosta Cabanillas, Lucía | |
dc.creator | Ramírez Angulo, Jaime | |
dc.creator | González Carvajal, Ramón | |
dc.date.accessioned | 2015-03-04T12:45:50Z | |
dc.date.available | 2015-03-04T12:45:50Z | |
dc.date.issued | 2011 | |
dc.identifier.issn | 1225-6463 | es |
dc.identifier.issn | 2233-7326 | es |
dc.identifier.uri | http://hdl.handle.net/11441/23355 | |
dc.description.abstract | A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW). | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.relation.ispartof | ETRI Journal, 33(3), 393-400 | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog integrated circuits | es |
dc.subject | CMOS buffer | en |
dc.subject | CMOS voltage follower | en |
dc.subject | Quasi-floating gate | en |
dc.title | Design of two-stage class AB CMOS buffers: a systematic approach | es |
dc.type | info:eu-repo/semantics/article | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Ingeniería Electrónica | es |
dc.relation.publisherversion | 10.4218/etrij.11.0110.0465 | es |
dc.relation.publisherversion | http://dx.doi.org/10.4218/etrij.11.0110.0465 | |
dc.identifier.doi | 10.4218/etrij.11.0110.0465 | |
dc.identifier.idus | https://idus.us.es/xmlui/handle/11441/23355 |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Design of two stage class AB ... | 1.224Mb | [PDF] | Ver/ | |