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dc.creatorCanelas, Antonioes
dc.creatorMoreira de Passos, Fabioes
dc.creatorLourenco, Nunoes
dc.creatorMartins, Ricardoes
dc.creatorRoca, Elisendaes
dc.creatorCastro López, Rafaeles
dc.creatorHorta, Nunoes
dc.creatorFernández Fernández, Francisco Vidales
dc.date.accessioned2022-04-06T11:33:53Z
dc.date.available2022-04-06T11:33:53Z
dc.date.issued2021
dc.identifier.citationCanelas, A., Moreira de Passos, F., Lourenco, N., Martins, R., Roca, E., Castro López, R.,...,Fernández Fernández, F.V. (2021). Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access, 9, 124152-124164.
dc.identifier.issn2169-3536es
dc.identifier.urihttps://hdl.handle.net/11441/131838
dc.description.abstractThis paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances’ calculation aims for the highest possible accuracy. A surrogate model calculates the performances for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical simulator calculates circuit- and system-level performances. Yield is calculated using Monte-Carlo (MC) analysis with the foundry-provided models without any model approximation. The computation of the circuit yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational requirements during the optimization. The yield of the elements not accurately evaluated is assigned using their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the methodology proposed in this work is compared against other methodologies that do not consider yield throughout the system’s complete hierarchy, demonstrating that it is necessary to consider it over the entire hierarchy to achieve robust optimal designs.es
dc.description.sponsorshipFundação para a Ciência e a Tecnologia del Ministério da Ciência, Tecnologia e Ensino Superior de Portugal (FCT/MCTES) UIDB/50008/2020es
dc.description.sponsorshipHorizonte 2020 de la Unión Europea. "Marie Skłodowska-Curie" nº 892431es
dc.formatapplication/pdfes
dc.format.extent13 p.es
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofIEEE Access, 9, 124152-124164.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectElectronic design automationes
dc.subjectMonte Carlo analysises
dc.subjectmultiobjective optimizationes
dc.subjectoptimization-based designes
dc.subjectradiofrequency integrated circuites
dc.titleHierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICses
dc.typeinfo:eu-repo/semantics/articlees
dc.type.versioninfo:eu-repo/semantics/publishedVersiones
dc.rights.accessrightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDUIDB/50008/2020es
dc.relation.projectIDH2020 nº892431es
dc.relation.publisherversionhttps://dx.doi.org/10.1109/ACCESS.2021.3110758es
dc.identifier.doi10.1109/ACCESS.2021.3110758es
dc.journaltitleIEEE Accesses
dc.publication.volumen9es
dc.publication.initialPage124152es
dc.publication.endPage124164es
dc.contributor.funderFundação para a Ciência e a Tecnologia. Portugales
dc.contributor.funderEuropean Union (UE)es
dc.contributor.funderEuropean Union (UE). H2020es

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