dc.creator | Canelas, Antonio | es |
dc.creator | Moreira de Passos, Fabio | es |
dc.creator | Lourenco, Nuno | es |
dc.creator | Martins, Ricardo | es |
dc.creator | Roca, Elisenda | es |
dc.creator | Castro López, Rafael | es |
dc.creator | Horta, Nuno | es |
dc.creator | Fernández Fernández, Francisco Vidal | es |
dc.date.accessioned | 2022-04-06T11:33:53Z | |
dc.date.available | 2022-04-06T11:33:53Z | |
dc.date.issued | 2021 | |
dc.identifier.citation | Canelas, A., Moreira de Passos, F., Lourenco, N., Martins, R., Roca, E., Castro López, R.,...,Fernández Fernández, F.V. (2021). Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access, 9, 124152-124164. | |
dc.identifier.issn | 2169-3536 | es |
dc.identifier.uri | https://hdl.handle.net/11441/131838 | |
dc.description.abstract | This paper presents an innovative yield-aware synthesis strategy based on a hierarchical
bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete
radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances’ calculation aims for the highest possible accuracy. A surrogate model calculates the performances
for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical
simulator calculates circuit- and system-level performances. Yield is calculated using Monte-Carlo (MC)
analysis with the foundry-provided models without any model approximation. The computation of the circuit
yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations
by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational
requirements during the optimization. The yield of the elements not accurately evaluated is assigned using
their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that
reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the
methodology proposed in this work is compared against other methodologies that do not consider yield
throughout the system’s complete hierarchy, demonstrating that it is necessary to consider it over the entire
hierarchy to achieve robust optimal designs. | es |
dc.description.sponsorship | Fundação para a Ciência e a Tecnologia del Ministério da Ciência, Tecnologia e Ensino Superior de Portugal (FCT/MCTES) UIDB/50008/2020 | es |
dc.description.sponsorship | Horizonte 2020 de la Unión Europea. "Marie Skłodowska-Curie" nº 892431 | es |
dc.format | application/pdf | es |
dc.format.extent | 13 p. | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Access, 9, 124152-124164. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Electronic design automation | es |
dc.subject | Monte Carlo analysis | es |
dc.subject | multiobjective optimization | es |
dc.subject | optimization-based design | es |
dc.subject | radiofrequency integrated circuit | es |
dc.title | Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | UIDB/50008/2020 | es |
dc.relation.projectID | H2020 nº892431 | es |
dc.relation.publisherversion | https://dx.doi.org/10.1109/ACCESS.2021.3110758 | es |
dc.identifier.doi | 10.1109/ACCESS.2021.3110758 | es |
dc.journaltitle | IEEE Access | es |
dc.publication.volumen | 9 | es |
dc.publication.initialPage | 124152 | es |
dc.publication.endPage | 124164 | es |
dc.contributor.funder | Fundação para a Ciência e a Tecnologia. Portugal | es |
dc.contributor.funder | European Union (UE) | es |
dc.contributor.funder | European Union (UE). H2020 | es |