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dc.creatorShang, Zeyies
dc.creatorVerlan, Sergeyes
dc.creatorZhang, Gexianges
dc.creatorMartínez del Amor, Miguel Ángeles
dc.creatorValencia Cabrera, Luises
dc.date.accessioned2021-11-29T12:10:53Z
dc.date.available2021-11-29T12:10:53Z
dc.date.issued2017
dc.identifier.citationShang, Z., Verlan, S., Zhang, G., Martínez del Amor, M.Á. y Valencia Cabrera, L. (2017). An Overview of Hardware Implementations of P Systems. En ACMC 2017: The 6th Asian Conference on Membrane Computing Chengdu, China: Xihua University.
dc.identifier.urihttps://hdl.handle.net/11441/127750
dc.description.abstractImplementing the P systems on parallel hardware is a re- search highlight in bio-inspired computing since the membrane comput- ing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware im- plementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is par- ticularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding prob- lem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problemes
dc.formatapplication/pdfes
dc.format.extent40es
dc.language.isoenges
dc.publisherXihua Universityes
dc.relation.ispartofACMC 2017: The 6th Asian Conference on Membrane Computing (2017).
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectMembrane computinges
dc.subjectP systemses
dc.subjectHardware Implementationes
dc.subjectField Programmable Gate Array (FPGA)es
dc.subjectCUDAes
dc.titleAn Overview of Hardware Implementations of P Systemses
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/publishedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ciencias de la Computación e Inteligencia Artificiales
dc.relation.publisherversionhttp://imcs.org.cn/img/(ACMC-2017)%206th.pdfes
dc.contributor.groupUniversidad de Sevilla. TIC193 : Computación Naturales
dc.eventtitleACMC 2017: The 6th Asian Conference on Membrane Computinges
dc.eventinstitutionChengdu, Chinaes
dc.relation.publicationplaceChengdu, Chinaes

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