A study on fundamental physical limitations of CMOS technologies

Abstract

In this work the problem of power dissipation for nano-CMOS technologies is addressed. The main focus is to analyze the physics behind the impossibility of scaling the subthreshold slope below 60 mV/decade. For that an NMOS transistor is studied. First, the carrier transport processes in subthreshold region are analyzed to understand the thermionic nature of their emission over the channel potential barrier. Then, the drain-source current is derived step by step from a diffusion current expression, procedure that has not been reported in the literature up to now. With that, it was proven that the subthreshold current is in fact a diffusion current and that the amount of current through the channel depends on the fraction of carriers able to thermionically surpass the barrier. From the subthreshold drain-source current, an analytical expression for the subthreshold slope SS is obtained, making use of its definition as the inverse of the transfer characteristic’s slope. After that, the different terms of SS are analyzed separately, and possible approaches to reduce its value are discussed. The fundamental nature of the 60 mV/dec limitation is proved to be a thermionic emission limitation. Finally, some emerging devices and their subthreshold slopes are analyzed and compared to the traditional MOSFET