Buscar
Mostrando ítems 1-8 de 8
Ponencia
SVITE: A Spike-Based VITE Neuro-Inspired Robot Controller
(Springer, 2013)
This paper presents an implementation of a neuro-inspired algorithm called VITE (Vector Integration To End Point) in FPGA in the spikes domain. VITE aims to generate a non-planned trajectory for reaching tasks in ...
Ponencia
Neuromorphic Real-Time Objects Tracking Using Address Event Representation and Silicon Retina
(Springer, 2011)
This paper presents a hierarchical neuromorphic system for tracking objects. We use AER (Address Event Representation) for transmitting and processing visual information provided by an asynchronous temporal contrast silicon ...
Ponencia
An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata
(Springer, 2011)
Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event- Representation (AER) is a neuromorphic communication protocol for ...
Ponencia
A FPGA Spike-Based Robot Controlled with Neuro-inspired VITE
(Springer, 2013)
This paper presents a spike-based control system applied to a fixed robotic platform. Our aim is to take a step forward to a future complete spikes processing architecture, from vision to direct motor actuation. This ...
Artículo
Inter-spike-intervals analysis of AER Poisson-like generator hardware
(Elsevier, 2007)
Address–Event–Representation (AER) is a communication protocol for transferring images between chips, originally developed for bio-inspired image-processing systems. Such systems may consist of a complicated hierarchical ...
Ponencia
AER Neuro-Inspired interface to Anthropomorphic Robotic Hand
(IEEE Computer Society, 2006)
Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for neuro-inspired processing systems (for example, image processing). ...
Artículo
Inter-spikes-intervals exponential and gamma distributions study of neuron firing rate for SVITE motor control model on FPGA
(Elsevier, 2015)
This paper presents a statistical study on a neuro-inspired spike-based implementation of the Vector-Integration-To-End-Point motor controller (SVITE) and compares its deterministic neuron-model stream of spikes with a ...
Ponencia
Frames-to-AER efficiency study based on CPUs Performance Counters
(IEEE Computer Society, 2010)
Image processing in digital computer systems usually considers the visual information as a sequence of frames. These frames are from photographs that capture reality for a short period of time. They are renewed and ...