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Mostrando ítems 11-20 de 26
Ponencia
Compact Calibration Circuit for Large Neuromorphic Arrays
(IEEE Computer Society, 2008)
Low current applications, like neuromorphic circuits, where operating currents can be as low as few nano amps or less, suffer from huge transistor mismatches, resulting in around or less than 1-bit precision. Here we ...
Ponencia
A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation
(IEEE Computer Society, 2000)
This paper presents a methodology for mismatch parameter extraction and mismatch simulation using conventional electrical simulators, like HSpice. A measurement and extraction procedure has been carefully designed to be ...
Ponencia
On Synthetic AER Generation
(IEEE, 2004-05)
In this paper several software methods for generating synthetic AER streams from images stored in a computer's memory are proposed and evaluated. Evaluation criteria cover execution time, distribution error and how they ...
Ponencia
Advanced Vision Processing Systems: Spike-Based Simulation and Processing
(Springer, 2009)
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it ...
Ponencia
Inter-spike-intervals Analysis of Poisson Like Hardware Synthetic AER Generation
(Springer, 2005)
Address-Event-Representation (AER) is a communication protocol for transferring images between chips, originally developed for bio-inspired image processing systems. Such systems may consist of a complicated hierarchical ...
Ponencia
Event based vision sensing and processing
(IEEE Computer Society, 2008)
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it ...
Ponencia
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
(Neural Information Processing Systems Foundation, 2005)
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-eventrepresentation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a ...
Ponencia
Fully Digital AER Convolution Chip for Vision Processing
(IEEE Computer Society, 2008)
We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It ...
Ponencia
A Mismatch Calibrated Bipolar Spatial Contrast AER Retina with Adjustable Contrast Threshold
(IEEE Computer Society, 2009)
Address Event Representation (AER) is an emergent technology for assembling modular multi-blocks bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since ...
Ponencia
Synthetic Generation of Events for Address-Event-Representation Communications
(Springer, 2002)
Address-Event-Representation (AER) is a communications protocol for transferring images between chips, originally developed for bio-inspired image processing systems. Such systems may consist of a complicated hierarchical ...