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Mostrando ítems 1-10 de 12
Ponencia
On scalable spiking convnet hardware for cortex-like visual sensory processing systems
(IEEE Computer Society, 2010)
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition ...
Ponencia
Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar
(IEEE, 2020)
Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are ...
Ponencia
Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices
(IEEE, 2021-04)
The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired ...
Ponencia
Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware
(IEEE Computer Society, 2010)
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition ...
Artículo
A 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
(IEEE Computer Society, 2011)
This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free ...
Ponencia
Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA
(IEEE Computer Society, 2018)
We have developed a fully configurable event-driven convolutional module with refractory period mechanism that can be used to implement arbitrary Convolutional Neural Networks (ConvNets) on FPGAs following a 2D array ...
Ponencia
Fully Digital AER Convolution Chip for Vision Processing
(IEEE Computer Society, 2008)
We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It ...
Ponencia
Event-driven stereo vision with orientation filters
(IEEE Computer Society, 2014)
The recently developed Dynamic Vision Sensors (DVS) sense dynamic visual information asynchronously and code it into trains of events with sub-micro second temporal resolution. This high temporal precision makes the ...
Artículo
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration
(IEEE, 2021-03)
Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired neuromorphic circuits. One ...
Artículo
Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations
(MDPI, 2019)
Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects ...