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Mostrando ítems 1-10 de 18
Artículo
Design considerations for integrated continuous-time chaotic oscillators
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant ...
Artículo
Switched-Current Chaotic Neurons
(Institution of Engineering and Technology, 1994)
The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks. They have been fabricated in a double-metal, single-poly 1.6µm CMOS technology. The neuron soma ...
Artículo
Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity ...
Artículo
A mixed-signal integrated circuit for FM-DCSK modulation
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental ...
Artículo
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
(Institute of Electrical and Electronics Engineers, 2011)
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the ...
Artículo
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits
(Institute of Electrical and Electronics Engineers, 2009)
We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the ...
Artículo
A Chaotic Switched-Capacitor Circuit for 1/f Noise Generation
(Institute of Electrical and Electronics Engineers, 1992)
A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order piecewise-finear discrete map which yields a hopping transition between regions of chaotic motions ...
Artículo
Integrated chaos generators
(Institute of Electrical and Electronics Engineers, 2002)
This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.
Artículo
Nonlinear switched-current CMOS IC for random signal generation
(Institution of Engineering and Technology, 1993)
A nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise. The circuit has been fabricated in a double-metal, single-poly 1.6µm CMOS technology ...
Artículo
System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
(Institute of Electrical and Electronics Engineers, 2017)
This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and ...