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Listar Artículos (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por autor "Núñez Martínez, Juan"
Mostrando ítems 1-14 de 14
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Artículo
A CMOS-compatible oscillation-based VO2 Ising machine solver
Maher, Olivier; Jiménez, Manuel; Delacour, Corentin; Harnack, Nele; Núñez Martínez, Juan; Avedillo de Juan, María José; Linares Barranco, Bernabé; Todri Sanial, Aida; Indiveri, Giacomo; Karg, Siegfried (Springer Nature, 2024-04-18)Phase-encoded oscillating neural networks offer compelling advantages over metal-oxide-semiconductor-based technology for ...
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Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2016)In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
Núñez Martínez, Juan; Ginés Arteaga, Antonio José; Peralías Macías, Eduardo; Rueda Rueda, Adoración (Springer, 2016)This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low ...
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Domino inspired MOBILE networks
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
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Efficient realisation of MOS-NDR threshold logic gates
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Wiley Open Access, 2009-11-05)A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms ...
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Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2014)Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ...
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Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs
Delgado Lozano, Ignacio María; Tena Sánchez, Erica; Núñez Martínez, Juan; Acosta Jiménez, Antonio José (IEEE, 2021)The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an ...
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Improving speed of tunnel FETs logic circuits
Avedillo de Juan, María José; Núñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2015)Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome ...
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Insights Into the Operation of Hyper-FET-Based Circuits
Avedillo de Juan, María José; Núñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2017)Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost ...
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Operation limits for RTD-based MOBILE circuits
Quintana Toledo, José María; Avedillo de Juan, María José; Núñez Martínez, Juan; Pettenghi Roldán, Héctor (IEEE, 2009-02)Resonant-tunneling-diode (RTD)-based monostable-bistable logic element (MOBILE) circuits operate properly in a certain ...
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Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown ...
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RTD-CMOS pipelined networks for reduced power consumption
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2011)The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit ...
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Artículo
Two-phase RTD-CMOS pipelined circuits
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) ...