Listar Artículos (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por autor "Espejo Meana, Servando Carlos"
Mostrando ítems 1-14 de 14
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A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) ...
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A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ...
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A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision
(Institute of Electrical and Electronics Engineers, 2003)A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has ...
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A Chaotic Switched-Capacitor Circuit for 1/f Noise Generation
(Institute of Electrical and Electronics Engineers, 1992)A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order ...
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A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors
(Institute of Electrical and Electronics Engineers, 2015)This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D ...
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A switched-capacitor broadband noise generator for CMOS VLSI
(Institution of Engineering and Technology, 1991)A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the ...
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ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
(Institute of Electrical and Electronics Engineers, 2004)Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible ...
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An 0.5-μm CMOS analog random access memory chip for TeraOPS speed multimedia video processing
(Institute of Electrical and Electronics Engineers, 1999)Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided ...
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CMOS optical-sensor array with high output current levels and automatic signal-range centring
(Institution of Engineering and Technology, 1994)A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range ...
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Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
(Institute of Electrical and Electronics Engineers, 1993)This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) ...
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Four-channel self-compensating single-slope ADC for space environments
(Institution of Electrical Engineers, 2014)A multichannel high-resolution single-slope analogue-to-digital converter (SS ADC) is presented that automatically compensates ...
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Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
(Institute of Electrical and Electronics Engineers, 2004)Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on ...
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SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing ...
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Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology
(Institute of Electrical and Electronics Engineers, 1994)This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. ...