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Artículo
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
(Springer, 2016)
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design ...
Artículo
MOST moderate-weak-inversion region as the optimum design zone for CMOS 2.4-GHz CS-LNAs
(Institute of Electrical and Electronics Engineers, 2014)
In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption ...