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Ponencia
A stored program 2/sup nd/ order/3-layer complex cell CNN-UM
(Institute of Electrical and Electronics Engineers, 2000)
A stored program 2/sup nd/ order/3-layer complex cell cellular neural network Universal Machine (CNN-UM) architecture is introduced. We discuss a number of phenomena that can be generated in this system by a single CNN ...
Artículo
nu MOS-based sorter for arithmetic applications
(Hindawi Publishing Corporation, 2000)
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8×8)-multiplier and a (15,4) counter which use a ...
Ponencia
Structure reconfigurability of the CNNUC3 for robust template operation
(Institute of Electrical and Electronics Engineers, 2000)
We demonstrate the importance of the reconfigurability of a 64/spl times/64 cells size CNN-UM chip. As we show, in such a high complexity mixed-signal VLSI circuit the switch and internal reference level reconfigurability ...
Ponencia
Reliable analysis of settling errors in SC integrators-application to the design of high-speed /spl Sigma//spl Delta/ modulators
(Institute of Electrical and Electronics Engineers, 2000)
This paper presents a detailed study on the transient response of SC integrators which takes into account the effects of amplifier finite gain-bandwidth product, slew-rate, and parasitic capacitances. Unlike previous models, ...
Ponencia
Experimental Characterization of IdleTones in Second-Order Bandpass ΣΔ Modulators
(2000)
This paper analyses the tonal behaviour of the quantization noise in second-order bandpass ΣΔ modulators. The analysis performed for lowpass modulators is extended to the bandpass case. As a result, closed form expressions ...
Ponencia
Object oriented image segmentation on the CNNUC3 chip
(Institute of Electrical and Electronics Engineers, 2000)
We show how a complex object oriented image analysis algorithm can be implemented on a CNNUM chip for video-coding. Besides the applied linear operations, several gray-scale nonlinear template operations are also emulated ...
Artículo
A programmable VLSI filter architecture for application in real-time vision processing systems
(World Scientific Publishing, 2000)
An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach is valid for any 2D filtering operation as ...
Ponencia
A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology
(2000)
This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, ...
Ponencia
High-order cascade multibit /spl Sigma//spl Delta/ modulators for xDSL applications
(Institute of Electrical and Electronics Engineers, 2000)
This paper explores the use of /spl Sigma//spl Delta/ modulators for A/D conversion in xDSL applications. Two high-order multibit architectures, the 2-1-1mb modulator and a novel 2-1-1-1mb cascade (MASH), are proposed to ...
Ponencia
Experimental demonstration of real-time image-processing using a VLSI analog programmable array processor
(SPIE- The International Society for Optical Engineering, 2000)
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitallyprogrammable analog parallel processing, and distributed image memory —cache— on a common silicon substrate. ...