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Mostrando ítems 1-10 de 24
Ponencia
Analog neural networks for real-time constrained optimization
(Institute of Electrical and Electronics Engineers, 1990)
Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI techniques are explored. Discrete-time analog techniques are considered due to their inherent accuracy, ...
Artículo
On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's
(Institute of Electrical and Electronics Engineers, 1990)
A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., ...
Ponencia
Hysteresis based neural oscillators for VLSI implementations
(Institute of Electrical and Electronics Engineers, 1991)
The actual tendency in most of the work that is being done in VLSI neural network research is to use the simplest possible models to perform the desired tasks. This yields to the use of sigmoidal type neurons that have ...
Ponencia
CMOS analog neural network systems based on oscillatory neurons
(Institute of Electrical and Electronics Engineers, 1992)
This paper addresses the design of two neural network systems based on the use of pulsing neurons. Each neuron is built as a simple voltage controlled oscillator (VCO) whose control voltage makes the circuit to oscillate ...
Artículo
A real-time clustering microchip neural engine
(Institute of Electrical and Electronics Engineers, 1996)
This paper presents an analog current-mode VLSI implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the popular ART1 algorithm, but has been modified resulting in a more VLSI-friendly ...
Ponencia
Modular analog continuous-time VLSI neural networks with on chip hebbian learning and analog storage
(Institute of Electrical and Electronics Engineers, 1992)
A modular analog circuit design approach for hardware implementations of neural networks is presented. This approach is based on the use of small transconductance multipliers as the main component, and is therefore called ...
Artículo
Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input
(Institute of Electrical and Electronics Engineers, 1999)
In low power current mode signal processing circuits it is often necessary to use current mirrors to replicate and amplify/attenuate current signals and clamp the voltage of nodes with high parasitic capacitances so that ...
Artículo
A general translinear principle for subthreshold MOS transistors
(Institute of Electrical and Electronics Engineers, 1999)
This paper revises the conditions under which the translinear principle can be fully exploited for MOS transistors operating in subthreshold. Due to the exponential nature of subthreshold MOS transistors, the translinear ...
Ponencia
A basic building block approach to CMOS design of analog neuro/fuzzy systems
(Institute of Electrical and Electronics Engineers, 1994)
Outlines a systematic approach to design fuzzy inference systems using analog integrated circuits in standard CMOS VLSI technologies. The proposed circuit building blocks are arranged in a layered neuro/fuzzy architecture ...
Artículo
An ART1 microchip and its use in multi-ART1 systems
(Institute of Electrical and Electronics Engineers, 1997)
Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. Such chip is able to cluster 100-b patterns into up to 18 categories at a speed of 1.8 μs per pattern. However, ...