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Mostrando ítems 31-40 de 58
Artículo
Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
(Institute of Electrical and Electronics Engineers, 1993)
This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are ...
Artículo
Robust high-accuracy high-speed continuous-time CMOS current comparator
(Institution of Engineering and Technology, 1997)
The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5pA) and high-speed for low input currents (8ns at 50nA). The new structure features a speed ...
Ponencia
Realization of non-linear templates using the CNNUC3 prototype
(Institute of Electrical and Electronics Engineers, 2000)
Demonstrates the processing capabilities of an analog programmable array processor chipMINUS/CNNUC3-which follows the cellular neural network Universal Machine computing paradigm. Due to its very advanced features and ...
Artículo
Global design of analog cells using statistical optimization techniques
(Springer, 1994)
We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU ...
Ponencia
Switched-current techniques for image processing Cellular Neural Networks in MOS VLSI
(Institute of Electrical and Electronics Engineers, 1992)
An architecture and related building blocks are presented for the realization of image processing tasks using current-mode analog-digital circuits. The architecture is based on the Cellular Neural Network paradigm while ...
Ponencia
Challenges in mixed-signal IC design of CNN chips in submicron CMOS
(Institute of Electrical and Electronics Engineers, 1998)
Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision system is due to the inherent parallelism of the former. In particular, the retina combines image ...
Ponencia
Weight-control strategy for programmable CNN chips
(Institute of Electrical and Electronics Engineers, 1994)
This paper describes a hybrid weight-control strategy for the VLSI realization of programmable CNNs, based on automatic adaptation of analog control signals to levels specified by digital words. This approach merges the ...
Ponencia
A processing element architecture for high-density focal plane analog programmable array processors
(Institute of Electrical and Electronics Engineers, 2002)
The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to ...
Ponencia
A multimode gray-scale CMOS optical sensor for visual computers
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural net) chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as ...
Ponencia
Programmable retinal dynamics in a CMOS mixed-signal array processor chip
(The International Society for Optical Engineering - SPIE, 2003)
The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully ...